公开(公告)号：JP2013153450A

公开(公告)日：2013-08-08

申请号：JP2013029067

申请日：2013-02-18

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： LAROCCA JUDITH ,  IRVINE CHRIS A ,  LEVIN JEFFREY A

IPC: G06F17/14 ,  H03M7/30 ,  G06F7/00 ,  G06T9/00 ,  H04N1/32 ,  H04N1/41 ,  H04N7/12 ,  H04N7/30 ,  H04N7/50

CPC classification number: G06F17/147

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus to determine a transform of a block of encoded data.SOLUTION: The block of encoded data comprises a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor and is configured, if enabled, to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and, if disabled, to transfer a second portion of processed data elements to at least one holding register.

Abstract translation: 要解决的问题：提供一种确定编码数据块的变换的装置。解码：编码数据块包括多个数据元素。 输入寄存器被配置为接收预定量的数据元素。 至少一个蝶形处理器耦合到输入寄存器，并且被配置为对所选择的数据元素对执行至少一个数学运算，以产生经处理的数据元素的输出。 至少一个中间寄存器耦合到蝶形处理器并且被配置为临时存储经处理的数据。 反馈回路耦合到中间寄存器和蝶形处理器，并且如果启用，则被配置为将经处理的数据元素的第一部分传送到适当的蝶形处理器以执行附加的数学运算，并且如果被禁用，则将第二部分 处理的数据元素至少一个保持寄存器。

公开(公告)号：JP2009177802A

公开(公告)日：2009-08-06

申请号：JP2008329261

申请日：2008-12-25

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： LAROCCA JUDITH ,  IRVINE CHRIS A ,  LEVIN JEFFREY A

IPC: G06F17/14 ,  H04N7/30 ,  G06F7/00 ,  G06T9/00 ,  H03M7/30 ,  H04N1/32 ,  H04N1/41 ,  H04N7/12 ,  H04N7/50

CPC classification number: G06F17/147

Abstract: PROBLEM TO BE SOLVED: To provide an efficient DCT (discrete cosine transform) computing circuit of DCT-encoded data. SOLUTION: An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations, and if disabled, is configured to transfer a second portion of processed data elements to at least one holding register. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供DCT编码数据的高效DCT（离散余弦变换）计算电路。

解决方案：输入寄存器被配置为接收预定量的数据元素。 至少一个蝶形处理器耦合到输入寄存器，并且被配置为对所选择的数据元素对执行至少一个数学运算，以产生经处理的数据元素的输出。 至少一个中间寄存器耦合到蝶形处理器并且被配置为临时存储经处理的数据。 反馈回路耦合到中间寄存器和蝶形处理器，并且如果启用，则被配置为将经处理的数据元素的第一部分传送到适当的蝶形处理器以执行附加的数学运算，并且如果被禁用则被配置为传送第二 处理的数据元素的一部分到至少一个保持寄存器。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：CA2791788C

公开(公告)日：2016-05-31

申请号：CA2791788

申请日：2002-05-15

Applicant: QUALCOMM INC

Inventor： LAROCCA JUDITH ,  IRVINE A CHRIS ,  LEVIN JEFFREY A

IPC: G06F17/14 ,  H04N19/60 ,  G06F7/00 ,  G06T9/00 ,  H03M7/30 ,  H04N1/32 ,  H04N1/41 ,  H04N7/12 ,  H04N7/30 ,  H04N7/50 ,  H04N19/433 ,  H04N19/436 ,  H04N19/625

Abstract: An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.

公开(公告)号：CA2446874C

公开(公告)日：2014-01-28

申请号：CA2446874

申请日：2002-05-15

Applicant: QUALCOMM INC

Inventor： LAROCCA JUDITH ,  IRVINE A CHRIS ,  LEVIN JEFFREY A

IPC: G06F17/14 ,  G06F7/00 ,  G06T9/00 ,  H03M7/30 ,  H04N1/32 ,  H04N1/41 ,  H04N7/12 ,  H04N7/30 ,  H04N7/50

Abstract: An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.

公开(公告)号：DE69633611D1

公开(公告)日：2004-11-18

申请号：DE69633611

申请日：1996-02-28

Applicant: QUALCOMM INC

Inventor： ZEHAVI EPHRAIM ,  MILLER S ,  LAROCCA JUDITH

IPC: H04B7/216 ,  H04J11/00 ,  H04J13/00 ,  H04J13/16 ,  H04L1/00 ,  H04L7/02 ,  H04L9/22 ,  H04J13/02

Abstract: A variable rate transmission system where a packet of variable is transmitted on a traffic channel if the capacity of the traffic channel is greater than or equal to the data rate of the packet. When the rate of the packet of variable rate data exceeds the capacity of the traffic channel, the packet is transmitted on a traffic channel and at least one overflow channel. Also described is a receiving system for receiving and reassembling the data transmitted on the traffic channel and at least one additional overflow channels.

公开(公告)号：HUE028871T2

公开(公告)日：2017-01-30

申请号：HUE03796288

申请日：2003-07-30

Applicant: QUALCOMM INC

Inventor： GOWINDASWAMY SENTHIL C/O QUALCOMM INCORPORATED ,  LEVIN JEFFREY A ,  LAROCCA JUDITH

IPC: G06T9/00 ,  H04N19/124

公开(公告)号：AU2002259268C1

公开(公告)日：2008-07-03

申请号：AU2002259268

申请日：2002-05-15

Applicant: QUALCOMM INC

Inventor： IRVINE CHRIS A ,  LEVIN JEFFREY A ,  LAROCCA JUDITH

IPC: G06F17/14 ,  G06F7/00 ,  G06T9/00 ,  H03M7/30 ,  H04N1/32 ,  H04N1/41 ,  H04N7/12 ,  H04N7/30 ,  H04N7/50

Abstract: An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.

公开(公告)号：AU2002259268B2

公开(公告)日：2007-11-29

申请号：AU2002259268

申请日：2002-05-15

Applicant: QUALCOMM INC

Inventor： IRVINE CHRIS A ,  LEVIN JEFFREY A ,  LAROCCA JUDITH

IPC: G06F17/14 ,  G06F7/00 ,  G06T9/00 ,  H03M7/30 ,  H04N1/32 ,  H04N1/41 ,  H04N7/12 ,  H04N7/30 ,  H04N7/50

Abstract: An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.

公开(公告)号：BR0209639A

公开(公告)日：2006-02-07

申请号：BR0209639

申请日：2002-05-15

Applicant: QUALCOMM INC

Inventor： LAROCCA JUDITH ,  IRVINE CHRIS A ,  LEVIN JEFFREY A

IPC: G06F17/14 ,  G06F7/00 ,  G06T9/00 ,  H03M7/30 ,  H04N1/32 ,  H04N1/41 ,  H04N7/12 ,  H04N7/30 ,  H04N7/50

Abstract: An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.

公开(公告)号：CA2213998A1

公开(公告)日：1996-09-06

申请号：CA2213998

申请日：1996-02-28

Applicant: QUALCOMM INC

Inventor： ZEHAVI EPHRAIM ,  LAROCCA JUDITH ,  MILLER DAVID S

IPC: H04B7/216 ,  H04J11/00 ,  H04J13/00 ,  H04J13/16 ,  H04L1/00 ,  H04L7/02 ,  H04L9/22 ,  H04J3/16

Abstract: The present invention discloses a variable rate transmission system wherein a packet of variable rate data is modulated in accordance with a traffic channel sequence supplied by a traffic PN generator (63) if the capacity of said traffic channel is greater than or equal to said data rate of the packet. If the capacity of said traffic channel is less than said data rate, the packet of variable rate data is modulated in accordance with the traffic channel sequence supplied by the traffic PN generator (63) and in accordance with at least one overflow channel sequence supplied by an overflow channel generator (65). The present invention further discloses a receiving system for receiving variable rate data where a received packet of variable rate data is demodulated in accordance with a traffic channel sequence supplied by a traffic PN generator (104) if the capacity of said traffic channel is greater than or equal to a data rate of said packet. If the capacity of said traffic channel is less than said data rate of the packet of variable rate data, the received packet is demodulated in accordance with a traffic channel sequence supplied by a traffic PN generator (104) and in accordance with at least one overflow channel sequence supplied by an overflow channel generator (120).