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公开(公告)号：KR20180056739A
公开(公告)日：2018-05-29
申请号：KR20187011322
申请日：2016-07-29
Applicant: QUALCOMM INC
Inventor： GU SHIQUN , KIM DAEIK DANIEL , NOWAK MATTHEW MICHAEL , KIM JONGHAE , YUN CHANGHAN HOBIE , LAN JE HSIUNG JEFFREY , BERDY DAVID FRANCIS
IPC: H01L27/12 , H01L21/304 , H01L21/306 , H01L21/762 , H01L21/768 , H01L21/8234
CPC classification number: H01L23/49894 , H01L21/304 , H01L21/30604 , H01L21/76251 , H01L21/76802 , H01L21/76877 , H01L21/76895 , H01L21/823481 , H01L21/84 , H01L23/528 , H01L23/66 , H01L27/088 , H01L27/092 , H01L27/1203 , H01L27/1222 , H01L27/1248 , H01L27/1255 , H01L27/1266 , H01L29/1087 , H01L29/66772 , H05K999/99
Abstract: 집적회로(IC)는유리기판상에제1 반도체디바이스를포함한다. 제1 반도체디바이스는벌크실리콘웨이퍼의제1 반도체지역을포함한다. IC는유리기판상에제2 반도체디바이스를포함한다. 제2 반도체디바이스는벌크실리콘웨이퍼의제2 반도체지역을포함한다. IC는제1 반도체지역과제2 반도체지역사이에기판관통트렌치(trench)를포함한다. 기판관통트렌치는벌크실리콘웨이퍼의표면을넘어배치된부분을포함한다.
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公开(公告)号：KR20180056686A
公开(公告)日：2018-05-29
申请号：KR20187010749
申请日：2016-09-20
Applicant: QUALCOMM INC
Inventor： VELEZ MARIO FRANCISCO , BERDY DAVID FRANCIS , YUN CHANGHAN HOBIE , KIM JONGHAE , ZUO CHENGJIE , KIM DAEIK DANIEL , LAN JE HSIUNG JEFFREY , MUDAKATTE NIRANJAN SUNIL , MIKULKA ROBERT PAUL
IPC: H01L23/498 , H01L23/00 , H01L23/13
CPC classification number: H01L24/17 , H01L23/13 , H01L23/49816 , H01L24/03 , H01L24/09 , H01L24/11 , H01L2224/023 , H01L2224/0905
Abstract: 웨이퍼레벨패키지 (wafer level package; WLP) 에서의집적회로디바이스는개선된솔더접합신뢰성을위하여접착제들로충전된캐비티들로제조된볼 그리드어레이 (ball grid array; BGA) 볼들을포함한다.
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公开(公告)号：KR20180070576A
公开(公告)日：2018-06-26
申请号：KR20187010277
申请日：2016-09-25
Applicant: QUALCOMM INC
Inventor： KIM DAEIK DANIEL , VELEZ MARIO FRANCISCO , YUN CHANGHAN HOBIE , MUDAKATTE NIRANJAN SUNIL , KIM JONGHAE , ZUO CHENGJIE , BERDY DAVID FRANCIS
CPC classification number: H01F27/2847 , H01F17/0013 , H01F41/04 , H01F41/041 , H01F2017/002 , H01F2017/004 , H03F15/00 , H03H7/0138
Abstract: 제1 만곡금속플레이트, 제1 만곡금속플레이트아래의그리고이와실질적으로수직정렬된제2 만곡금속플레이트, 및제1 만곡금속플레이트와제2 만곡금속플레이트사이에수직으로정렬된제1 세장형비아를포함하며, 제1 세장형비아는제1 만곡금속플레이트를제2 만곡금속플레이트에전도결합하도록구성되고, 적어도약 2 대 1인제1 세장형비아의폭 대높이의종횡비를갖는인덕터디바이스가개시된다.
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公开(公告)号：KR20180042448A
公开(公告)日：2018-04-25
申请号：KR20187010373
申请日：2016-07-29
Applicant: QUALCOMM INC
Inventor： LAN JE HSIUNG JEFFREY , MUDAKATTE NIRANJAN SUNIL , YUN CHANGHAN HOBIE , KIM DAEIK DANIEL , ZUO CHENGJIE , BERDY DAVID FRANCIS , VELEZ MARIO FRANCISCO , KIM JONGHAE
IPC: H01L23/15 , H01L21/48 , H01L23/498 , H01L23/522 , H01L27/01 , H01L49/02
CPC classification number: H01L27/01 , H01L21/4846 , H01L23/15 , H01L23/49816 , H01L23/49822 , H01L23/5223 , H01L23/5227 , H01L28/10 , H01L28/75 , H01L2224/11
Abstract: 디바이스는유리기판및 캐패시터를포함한다. 캐패시터는제1 전극에커플링된제1 금속, 유전체구조, 및캐패시터의제2 전극을포함하는비아구조를포함한다. 제1 금속구조는유전체구조에의해비아구조로부터분리된다.
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5.发明专利
公开(公告)号：CA3004764C
公开(公告)日：2021-01-26
申请号：CA3004764
申请日：2016-12-05
Applicant: QUALCOMM INC
Inventor： YUN CHANGHAN HOBIE , KIM DAEIK DANIEL , VELEZ MARIO FRANCISCO , ZUO CHENGJIE , BERDY DAVID FRANCIS , KIM JONGHAE
IPC: H03H7/46
Abstract: A multiplexer structure (500) includes a passive substrate (508). The multiplexer structure (500) may also include a high band filter (502) on the passive substrate. The high band filter (502) may include a 2D planar spiral inductor(s) (530, 540) on the passive substrate. The multiplexer structure (500) may further include a low band filter (504) on the passive substrate. The low band filter (504) may include a 3D through-substrate inductor (510, 520) and a first capacitor(s) on the passive substrate. The multiplexer structure (500) may also include a through substrate via(s) (VIA) coupling the high band filter (502) and the low band filter (504).
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Patent Agency Ranking
公开(公告)号：CA2999507A1
公开(公告)日：2017-04-20
申请号：CA2999507
申请日：2016-09-25
Applicant: QUALCOMM INC
Inventor： KIM DAEIK DANIEL , VELEZ MARIO FRANCISCO , YUN CHANGHAN HOBIE , MUDAKATTE NIRANJAN SUNIL , KIM JONGHAE , ZUO CHENGJIE , BERDY DAVID FRANCIS
Abstract: Disclosed is an inductor device including a first curved metal plate, a second curved metal plate below and substantially vertically aligned with the first curved metal plate, and a first elongated via vertically aligned between the first curved metal plate and the second curved metal plate, the first elongated via configured to conductively couple the first curved metal plate to the second curved metal plate and having an aspect ratio of a width to a height of the first elongated via of at least approximately 2 to 1.
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公开(公告)号：CA3010589A1
公开(公告)日：2017-08-10
申请号：CA3010589
申请日：2016-12-21
Applicant: QUALCOMM INC
Inventor： KIM DAEIK DANIEL , VELEZ MARIO FRANCISCO , YUN CHANGHAN HOBIE , ZUO CHENGJIE , BERDY DAVID FRANCIS , KIM JONGHAE , MUDAKATTE NIRANJAN SUNIL
Abstract: A conductive bump assembly may include a passive substrate. The conductive bump assembly may also include a conductive bump pad supported by the passive substrate and surrounded by a first passivation layer opening. The conductive bump assembly may further include a second passivation layer opening on the passive substrate. The second passivation layer opening may be merged with the first passivation layer opening surrounding the conductive bump pad proximate an edge of the passive substrate. The conductive bump assembly may also include a conductive bump on the conductive bump pad.
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公开(公告)号：ES2797149T3
公开(公告)日：2020-12-01
申请号：ES16781918
申请日：2016-09-25
Applicant: QUALCOMM INC
Inventor： KIM DAEIK DANIEL , VELEZ MARIO FRANCISCO , YUN CHANGHAN HOBIE , MUDAKATTE NIRANJAN SUNIL , KIM JONGHAE , ZUO CHENGJIE , BERDY DAVID FRANCIS
Abstract: Un dispositivo inductor (400), que comprende: un primer medio conductor plano (410); un segundo medio conductor plano (420) debajo de y alineado de manera sustancialmente vertical con el primer medio conductor (410); un tercer medio conductor plano (430) coubicado entre el primer medio conductor (410) y el segundo medio conductor (420); una primera vía alargada (414) alineada verticalmente entre el primer medio conductor (410) y el tercer medio conductor (430), donde la primera vía alargada (414) está configurada para acoplar de manera conductiva el primer medio conductor (410) al tercer medio conductor (430) y tiene una relación de aspecto de una longitud, medida en la dirección de dicho plano, a una altura de la primera vía alargada (414) de al menos aproximadamente 2 a 1, donde la longitud de la primera vía alargada (414) sigue sustancialmente una curva del primer medio conductor (410) y del tercer medio conductor (420); y una segunda vía alargada (424) alineada verticalmente entre el tercer medio conductor (430) y el segundo medio conductor (420), donde la segunda vía alargada (424) está configurada para acoplar de manera conductiva el tercer medio conductor (430) al segundo medio conductor (420) y tiene una relación de aspecto de una longitud a una altura de al menos aproximadamente 2 a 1, donde la longitud de la segunda vía alargada (424) sigue sustancialmente una curva del tercer medio conductor (430) y del segundo medio conductor (420); en el que cada uno del primer medio conductor (410), el segundo medio conductor (420) y el tercer medio conductor (430) consisten en múltiples capas metálicas.
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公开(公告)号：HUE049466T2
公开(公告)日：2020-09-28
申请号：HUE16781918
申请日：2016-09-25
Applicant: QUALCOMM INC
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10.发明专利
公开(公告)号：CA3004764A1
公开(公告)日：2017-07-06
申请号：CA3004764
申请日：2016-12-05
Applicant: QUALCOMM INC
Inventor： YUN CHANGHAN HOBIE , KIM DAEIK DANIEL , VELEZ MARIO FRANCISCO , ZUO CHENGJIE , BERDY DAVID FRANCIS , KIM JONGHAE
IPC: H03H7/46
Abstract: A multiplexer structure (500) includes a passive substrate (508). The multiplexer structure (500) may also include a high band filter (502) on the passive substrate. The high band filter (502) may include a 2D planar spiral inductor(s) (530, 540) on the passive substrate. The multiplexer structure (500) may further include a low band filter (504) on the passive substrate. The low band filter (504) may include a 3D through-substrate inductor (510, 520) and a first capacitor(s) on the passive substrate. The multiplexer structure (500) may also include a through substrate via(s) (VIA) coupling the high band filter (502) and the low band filter (504).
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