公开(公告)号：AT521903T

公开(公告)日：2011-09-15

申请号：AT08770869

申请日：2008-06-12

Applicant: QUALCOMM INC

Inventor： MADDALI SRINIVAS

IPC: G01R31/3187

Abstract: This disclosure describes an integrated circuit with self-test features for validating functionality of external interfaces. Example external interfaces include memory interfaces and bus interfaces, such as a peripheral component interconnect (PCI) bus, an advanced high-performance bus (AHB), an advanced extensible interface (AXI) bus, and other external interfaces that operate a high frequency, e.g., 200 MHz or greater. Test logic may be embedded on the integrated circuit and configured to validate functionality of external interfaces while receiving power and non-test signals from external test equipment. Thus, external test equipment may not supply high frequency test signals to the integrated circuit. The external test equipment may, however, independently validate functionality of a pin interface of the integrated circuit. As a result, the integrated circuit may reduce cost and time required to verify functionality and timing of the external interfaces.

公开(公告)号：DE602006013023D1

公开(公告)日：2010-04-29

申请号：DE602006013023

申请日：2006-11-10

Applicant: QUALCOMM INC

Inventor： SRINIVAS VAISHNAV ,  KAPOOR SANAT ,  MADDALI SRINIVAS ,  MOHAN VIVEK

IPC: G06F13/16 ,  G11C7/10

公开(公告)号：ES2719544T3

公开(公告)日：2019-07-11

申请号：ES10754172

申请日：2010-03-19

Applicant: QUALCOMM INC

Inventor： MADDALI SRINIVAS ,  SRIRAMAGIRI DEEPTI

IPC: G06F13/16 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G11C11/408

Abstract: Un controlador de memoria (12), que comprende: un controlador configurado para acceder al menos a una ubicación de memoria correspondiente a al menos una página de memoria (29) contenida en cada uno de una pluralidad de bancos de memoria (28) de acuerdo con una configuración de acceso a memoria proporcionada para cada uno de la pluralidad de bancos de memoria; en donde la configuración de acceso a memoria permite que cada uno de una pluralidad de bancos de memoria cierre o deje abierta la al menos una página de memoria y en donde la configuración de acceso a memoria para cada uno de la pluralidad de bancos de memoria se configura como una configuración estática almacenada en uno o más registros internos; el controlador está configurado además para determinar si la configuración de acceso a memoria almacenada en uno o más registros internos para un banco de memoria entre la pluralidad de bancos de memoria se anulará temporalmente sin cambiar la configuración de acceso a memoria; en donde el controlador comprende además el primer y el segundo registro de configuración de acceso a memoria dinámica (174, 176), teniendo cada uno un bit para cada uno de la pluralidad de bancos de memoria, en donde los bits en el primer registro de configuración de acceso a memoria dinámica se configuran para permitir que el controlador de memoria anule una página de memoria configurada para cerrarse después del acceso y los bits en el segundo registro de configuración de acceso a memoria dinámica están configurados para permitir que el controlador de memoria anule una página de memoria configurada para dejarla abierta después del acceso; y en donde el controlador está configurado para cerrar o dejar abierta la al menos una página de memoria en base a la configuración de acceso a memoria proporcionada para cada uno de la pluralidad de bancos de memoria y en base a los bits en los primer y segundo registros de configuración de acceso a memoria dinámica.

公开(公告)号：HUE041677T2

公开(公告)日：2019-05-28

申请号：HUE10754172

申请日：2010-03-19

Applicant: QUALCOMM INC

Inventor： MADDALI SRINIVAS ,  SRIRAMAGIRI DEEPTI

IPC: G06F13/16 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08

公开(公告)号：AT461487T

公开(公告)日：2010-04-15

申请号：AT06839836

申请日：2006-11-10

Applicant: QUALCOMM INC

Inventor： SRINIVAS VAISHNAV ,  KAPOOR SANAT ,  MADDALI SRINIVAS ,  MOHAN VIVEK

IPC: G06F13/16 ,  G11C7/10

公开(公告)号：WO2008157246A8

公开(公告)日：2010-04-15

申请号：PCT/US2008066744

申请日：2008-06-12

Applicant: QUALCOMM INC ,  MADDALI SRINIVAS

Inventor： MADDALI SRINIVAS

IPC: G01R31/3187

CPC classification number: G01R31/3187 ,  G06F11/27

Abstract: This disclosure describes an integrated circuit with self-test features for validating functionality of external interfaces. Example external interfaces include memory interfaces and bus interfaces, such as a peripheral component interconnect (PCI) bus, an advanced high-performance bus (AHB), an advanced extensible interface (AXI) bus, and other external interfaces that operate a high frequency, e.g., 200 MHz or greater. Test logic may be embedded on the integrated circuit and configured to validate functionality of external interfaces while receiving power and non-test signals from external test equipment. Thus, external test equipment may not supply high frequency test signals to the integrated circuit. The external test equipment may, however, independently validate functionality of a pin interface of the integrated circuit. As a result, the integrated circuit may reduce cost and time required to verify functionality and timing of the external interfaces.

Abstract translation: 本公开描述了具有用于验证外部接口的功能的自检特征的集成电路。 示例外部接口包括存储器接口和总线接口，例如外围组件互连（PCI）总线，高级高性能总线（AHB），高级可扩展接口（AXI）总线和操作高频的其他外部接口， 例如，200MHz或更大。 测试逻辑可以嵌入在集成电路中，并被配置为在从外部测试设备接收电力和非测试信号的同时验证外部接口的功能。 因此，外部测试设备可能不会向集成电路提供高频测试信号。 然而，外部测试设备可以独立地验证集成电路的引脚接口的功能。 结果，集成电路可以降低验证外部接口的功能和定时所需的成本和时间。

公开(公告)号：WO2010108096A3

公开(公告)日：2011-01-13

申请号：PCT/US2010027981

申请日：2010-03-19

Applicant: QUALCOMM INC ,  MADDALI SRINIVAS ,  SRIRAMAGIRI DEEPTI VIJAYALAKSHMI

Inventor： MADDALI SRINIVAS ,  SRIRAMAGIRI DEEPTI VIJAYALAKSHMI

IPC: G06F13/16 ,  G06F12/06 ,  G06F12/08

CPC classification number: G11C11/4085 ,  G06F12/0215 ,  G06F12/0607 ,  G06F12/0623 ,  G06F13/1694

Abstract: A configurable memory access controller and related systems and methods. In embodiments described herein, the configurable memory controller is adapted to provide a separate memory access configuration for each of a plurality of memory banks in a given memory system. The memory access configuration provided for each memory bank can either be to leave open or close at least one memory page in each memory bank. In this manner, a memory access configuration can be provided for each memory bank on an individualized basis to optimize memory access times based on the type of data activity in each memory bank. In embodiments described herein, the memory controller can also be configured to allow for dynamic configuration of one or more memory banks. Dynamic configuration involves changing or overriding the memory access configuration for a particular memory bank to optimize memory access times.

Abstract translation: 可配置的存储器访问控制器及相关系统和方法。 在本文描述的实施例中，可配置存储器控制器适于为给定存储器系统中的多个存储器组中的每一个提供单独的存储器访问配置。 为每个存储体提供的存储器访问配置可以是在每个存储体中保持打开或关闭至少一个存储器页。 以这种方式，可以基于个别的基础为每个存储体提供存储器访问配置，以基于每个存储体中的数据活动的类型优化存储器访问时间。 在这里描述的实施例中，存储器控制器还可以被配置为允许一个或多个存储体的动态配置。 动态配置涉及更改或覆盖特定存储库的存储器访问配置，以优化存储器访问时间。

公开(公告)号：EP2409235A4

公开(公告)日：2012-05-09

申请号：EP10754172

申请日：2010-03-19

Applicant: QUALCOMM INC

Inventor： MADDALI SRINIVAS ,  SRIRAMAGIRI DEEPTI VIJAYALAKSHMI

IPC: G06F13/16 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G11C11/408

CPC classification number: G11C11/4085 ,  G06F12/0215 ,  G06F12/0607 ,  G06F12/0623 ,  G06F13/1694

Abstract: A configurable memory access controller and related systems and methods. In embodiments described herein, the configurable memory controller is adapted to provide a separate memory access configuration for each of a plurality of memory banks in a given memory system. The memory access configuration provided for each memory bank can either be to leave open or close at least one memory page in each memory bank. In this manner, a memory access configuration can be provided for each memory bank on an individualized basis to optimize memory access times based on the type of data activity in each memory bank. In embodiments described herein, the memory controller can also be configured to allow for dynamic configuration of one or more memory banks. Dynamic configuration involves changing or overriding the memory access configuration for a particular memory bank to optimize memory access times.

公开(公告)号：WO2008143950A3

公开(公告)日：2009-01-29

申请号：PCT/US2008006256

申请日：2008-05-14

Applicant: QUALCOMM INC ,  MADDALI SRINIVAS ,  BEBAL ARSHAD ,  KUO TOM TSOWEI ,  YANG TUN

Inventor： MADDALI SRINIVAS ,  BEBAL ARSHAD ,  KUO TOM TSOWEI ,  YANG TUN

IPC: G06F12/04 ,  G06F9/445 ,  G06F13/38

CPC classification number: G06F12/04 ,  G11C16/20

Abstract: Methods and apparatuses are presented for memory page size auto detection. A method for automatically determining a page size of a memory device includes receiving page size extents of the memory device, determining a bus width of the memory device, detecting a number of pages having an automatic detection marker, and determining the page size of the memory device based upon the detected number of pages and the received page size extents. An apparatus for automatically determining page size detection includes logic for performing the above presented method.

Abstract translation: 提出了用于存储器页面大小自动检测的方法和装置。 一种用于自动确定存储器设备的页面大小的方法包括接收存储器设备的页面大小范围，确定存储器设备的总线宽度，检测具有自动检测标记的页数，以及确定存储器的页面大小 设备基于检测到的页面数量和接收到的页面大小范围。 用于自动确定页面大小检测的装置包括用于执行上述方法的逻辑。

公开(公告)号：WO2007059443A3

公开(公告)日：2007-07-26

申请号：PCT/US2006060797

申请日：2006-11-10

Applicant: QUALCOMM INC ,  SRINIVAS VAISHNAV ,  KAPOOR SANAT ,  MADDALI SRINIVAS ,  MOHAN VIVEK

Inventor： SRINIVAS VAISHNAV ,  KAPOOR SANAT ,  MADDALI SRINIVAS ,  MOHAN VIVEK

IPC: G06F13/16 ,  G11C7/10

CPC classification number: G11C7/1051

Abstract: This disclosure describes a clock circuit for a memory controller. The described circuit uses a processor clock signal to generate an input clock signal for use during write operations to the memory, or to generate a feedback clock signal for use during read operations from the memory. The circuit is particularly applicable to mobile wireless devices that include memories that do not generate a strobe. The clock circuit may comprise a driver in series with a resistor element that generates an input clock signal for input to a memory, and a resistor-capacitor (RC) filter in series with a receiver that generates a feedback clock signal for output from the memory, wherein an input to the RC filter is tapped between the driver and the resistor element.

Abstract translation: 本公开描述了用于存储器控制器的时钟电路。 所描述的电路使用处理器时钟信号来产生输入时钟信号以在对存储器的写入操作期间使用，或者产生反馈时钟信号以在从存储器读取操作期间使用。 该电路特别适用于包括不产生频闪的存储器的移动无线设备。 时钟电路可以包括与产生用于输入到存储器的输入时钟信号的电阻器元件串联的驱动器和与接收器串联的电阻器 - 电容器（RC）滤波器，所述接收器产生用于从存储器输出的反馈时钟信号 其中，在所述驱动器和所述电阻器元件之间分接到所述RC滤波器的输入。