公开(公告)号：AT461487T

公开(公告)日：2010-04-15

申请号：AT06839836

申请日：2006-11-10

Applicant: QUALCOMM INC

Inventor： SRINIVAS VAISHNAV ,  KAPOOR SANAT ,  MADDALI SRINIVAS ,  MOHAN VIVEK

IPC: G06F13/16 ,  G11C7/10

公开(公告)号：ES2326903T3

公开(公告)日：2009-10-21

申请号：ES05817276

申请日：2005-11-07

Applicant: QUALCOMM INC

Inventor： PATEL JAGRUT VILISKUMAR ,  BULLARD GREGORY ,  KAPOOR SANAT

IPC: G01R31/3193

Abstract: Un procedimiento de calibración de un circuito integrado para un componente electrónico, el circuito integrado teniendo un reloj de sistema, comprendiendo el procedimiento: generar un reloj externo en el circuito integrado, teniendo el reloj externo un retardo programable respecto del reloj de sistema; proporcionar un reloj externo a partir del circuito integrado al componente electrónico para soportar las comunicaciones con el mismo; caracterizado por los pasos de determinar (600) un intervalo de retardo entre el reloj de sistema y el reloj externo en el que el circuito integrado y el componente electrónico puedan comunicar; y programar (700) el reloj externo con una de una pluralidad de valores de retardo predeterminados en base al intervalo de retardo.

公开(公告)号：DE602006013023D1

公开(公告)日：2010-04-29

申请号：DE602006013023

申请日：2006-11-10

Applicant: QUALCOMM INC

Inventor： SRINIVAS VAISHNAV ,  KAPOOR SANAT ,  MADDALI SRINIVAS ,  MOHAN VIVEK

IPC: G06F13/16 ,  G11C7/10

公开(公告)号：AT430320T

公开(公告)日：2009-05-15

申请号：AT05817276

申请日：2005-11-07

Applicant: QUALCOMM INC

Inventor： PATEL JAGRUT VILISKUMAR ,  BULLARD GREGORY ,  KAPOOR SANAT

IPC: G01R31/3193

Abstract: An electronic device comprises an electronic component and an integrated circuit, wherein the integrated circuit is configured to generate a system clock and an external clock having a programmable delay from the system clock, provide the external clock to the electronic component, determine a delay range between system clock and the external clock in which the integrated circuit and the electronic component can communicate, and program the external clock with one of a plurality of predetermined delay values based on the delay range.

公开(公告)号：CA2586445A1

公开(公告)日：2006-05-18

申请号：CA2586445

申请日：2005-11-04

Applicant: QUALCOMM INC

Inventor： PATEL JAGRUT V ,  PRABHAKARAN RAJEEV ,  BULLARD GREGORY ,  KAPOOR SANAT

IPC: G06F1/08

Abstract: Systems and techniques are disclosed relating to adapting the frequency of an electronic device comprising an integrated circuit and an electronic component to improve performance. The integrated circuit determines a set of frequency plans, each corresponding to a distribution of delay range highest passing values and one of a set of frequencies at which the electronic device can operate. Based on communication with the electronic component, the integrated circuit implements a preferred frequency plan.

公开(公告)号：DE602005014264D1

公开(公告)日：2009-06-10

申请号：DE602005014264

申请日：2005-11-07

Applicant: QUALCOMM INC

Inventor： PATEL JAGRUT VILISKUMAR ,  BULLARD GREGORY ,  KAPOOR SANAT

IPC: G01R31/3193

Abstract: An electronic device comprises an electronic component and an integrated circuit, wherein the integrated circuit is configured to generate a system clock and an external clock having a programmable delay from the system clock, provide the external clock to the electronic component, determine a delay range between system clock and the external clock in which the integrated circuit and the electronic component can communicate, and program the external clock with one of a plurality of predetermined delay values based on the delay range.

公开(公告)号：MX2007005484A

公开(公告)日：2007-07-16

申请号：MX2007005484

申请日：2005-11-07

Applicant: QUALCOMM INC

Inventor： PATEL JAGRUT VILISKUMAR ,  BULLARD GREGORY ,  KAPOOR SANAT

IPC: G11C29/50 ,  G01R31/3193

Abstract: Un dispositivo electronico comprende un componente electronico y un circuito integrado, en donde el circuito integrado esta configurado para generar un reloj de sistema y un reloj externo que tiene un retraso programable a partir del reloj del sistema, proveer el reloj externo al componente electronico, determinar un rango de retraso entre el reloj del sistema y el reloj externo en donde el circuito integrado y el componente electronico pueden establecer comunicacion, y programar el reloj externo con uno de una pluralidad de valores de retraso predeterminados con base en el rango de retraso.

公开(公告)号：BRPI0416892A

公开(公告)日：2007-03-06

申请号：BRPI0416892

申请日：2004-11-24

Applicant: QUALCOMM INC

Inventor： PATEL JAGRUT V ,  CHUN DEXTER TAMIO ,  BULLARD GREGORY ,  SANKURATRI RAGHU ,  PRABHAKARAN RAJEEV ,  KAPOOR SANAT

IPC: G01R35/00 ,  G06F1/14

Abstract: Systems and techniques are disclosed relating to calibrating an integrated circuit to an electronic component. The systems and techniques include an integrated circuit configured to generate a system clock and an external clock having a programmable delay from the system clock. The integrated circuit may also be configured to provide the external clock to the electronic component to support communications therewith, communicate with the electronic component, and calibrate the external clock delay as a function of the communications.

公开(公告)号：CA2586537A1

公开(公告)日：2006-05-18

申请号：CA2586537

申请日：2005-11-07

Applicant: QUALCOMM INC

Inventor： KAPOOR SANAT ,  BULLARD GREGORY ,  PATEL JAGRUT VILISKUMAR

IPC: G01R31/3193 ,  G11C29/50

Abstract: An electronic device comprises an electronic component and an integrated circuit, wherein the integrated circuit is configured to generate a system clock and an external clock having a programmable delay from the system clock, provide the external clock to the electronic component, determine a delay range between system clock and the external clock in which the integrated circuit and the electronic component can communicate, and program the external clock with one of a plurality of predetermined delay values based on the delay range.

公开(公告)号：WO2007059443A3

公开(公告)日：2007-07-26

申请号：PCT/US2006060797

申请日：2006-11-10

Applicant: QUALCOMM INC ,  SRINIVAS VAISHNAV ,  KAPOOR SANAT ,  MADDALI SRINIVAS ,  MOHAN VIVEK

Inventor： SRINIVAS VAISHNAV ,  KAPOOR SANAT ,  MADDALI SRINIVAS ,  MOHAN VIVEK

IPC: G06F13/16 ,  G11C7/10

CPC classification number: G11C7/1051

Abstract: This disclosure describes a clock circuit for a memory controller. The described circuit uses a processor clock signal to generate an input clock signal for use during write operations to the memory, or to generate a feedback clock signal for use during read operations from the memory. The circuit is particularly applicable to mobile wireless devices that include memories that do not generate a strobe. The clock circuit may comprise a driver in series with a resistor element that generates an input clock signal for input to a memory, and a resistor-capacitor (RC) filter in series with a receiver that generates a feedback clock signal for output from the memory, wherein an input to the RC filter is tapped between the driver and the resistor element.

Abstract translation: 本公开描述了用于存储器控制器的时钟电路。 所描述的电路使用处理器时钟信号来产生输入时钟信号以在对存储器的写入操作期间使用，或者产生反馈时钟信号以在从存储器读取操作期间使用。 该电路特别适用于包括不产生频闪的存储器的移动无线设备。 时钟电路可以包括与产生用于输入到存储器的输入时钟信号的电阻器元件串联的驱动器和与接收器串联的电阻器 - 电容器（RC）滤波器，所述接收器产生用于从存储器输出的反馈时钟信号 其中，在所述驱动器和所述电阻器元件之间分接到所述RC滤波器的输入。