公开(公告)号：CA2476913A1

公开(公告)日：2003-09-04

申请号：CA2476913

申请日：2003-02-21

Applicant: QUALCOMM INC

Inventor： HUSSEINI JALAL ,  LI TAO ,  ARCEO JULIO ,  KANG INYUP ,  WEI JIAN ,  OISHI MOTO ,  RODRIGUES BRIAN ,  MEAGHER BRUCE ,  HIGGINS RICHARD

IPC: G06F11/10 ,  G06F3/06 ,  G06F7/00 ,  G06F12/00 ,  G06F12/06 ,  G06F12/16 ,  G06F13/16 ,  G06F13/28 ,  G11C7/00 ,  G11C7/10 ,  G11C14/00 ,  G11C16/04 ,  H04B7/00

Abstract: Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specifi c design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage unit s, and a data bus coupled to both storage units and the EMI unit. The two stora ge units are implemented external to the ASIC, and each storage unit is operabl e to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.

公开(公告)号：AU2003213196A1

公开(公告)日：2003-09-09

申请号：AU2003213196

申请日：2003-02-21

Applicant: QUALCOMM INC

Inventor： ARCEO JULIO ,  HUSSEINI JALAL ,  LI TAO ,  MEAGHER BRUCE ,  HIGGINS RICHARD ,  OISHI MOTO ,  RODRIGUES BRIAN ,  WEI JIAN ,  KANG INYUP

IPC: G06F11/10 ,  G06F3/06 ,  G06F7/00 ,  G06F12/00 ,  G06F12/06 ,  G06F12/16 ,  G06F13/16 ,  G06F13/28 ,  G11C7/00 ,  G11C7/10 ,  G11C14/00 ,  G11C16/04 ,  H04B7/00

Abstract: Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage units, and a data bus coupled to both storage units and the EMI unit. The two storage units are implemented external to the ASIC, and each storage unit is operable to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.