公开(公告)号：SG151304A1

公开(公告)日：2009-04-30

申请号：SG2009020108

申请日：2005-03-11

Applicant: QUALCOMM INC

Inventor： SIH GILBERT CHRISTOPHER ,  SAKAMAKI CHARLES E ,  HSU DE D ,  WEI JIAN ,  HIGGINS RICHARD

IPC: G06F12/08

Abstract: CACHED MEMORY SYSTEM AND CACHE CONTROLLER FOR EMBEDDED DIGITAL SIGNAL PROCESSOR A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.

公开(公告)号：HK1058256A1

公开(公告)日：2004-05-07

申请号：HK04100929

申请日：2004-02-12

Applicant: QUALCOMM INC

Inventor： LUDWIN ALBERT SCOTT ,  SHI GUANMING ,  HIGGINS RICHARD ,  BAYLEY GWAIN

IPC: G06F20060101 ,  G06F9/45 ,  G06F13/10 ,  H04B7/26

Abstract: The virtual device architecture provides physical and logical device drivers for interfacing software programs executing on a microprocessor of the mobile telephone of a wireless communication system with any of a wide variety of hardware devices connectable within the mobile telephone. The logical device drivers convert commands received from the software applications to commands appropriate for use by selected hardware devices. The physical device drivers receive the converted commands from the logical device drivers and in response to the received commands directly control the selected hardware devices. In one example described herein, the logical device drivers provide translation of core commands necessary to control the selected hardware devices and extended commands for enhanced control of the hardware devices. The logical device drivers operate to convert the extended commands into core commands prior to forwarding the commands to the physical device drivers. By providing logical and physical drivers for use with peripheral devices, the need to provide different versions of software executing on the microprocessor to accommodate different types of peripheral devices is substantially eliminated resulting in a considerable reduction in time and cost associated with developing, maintaining and upgrading software. By providing logical device drivers capable of accommodating both core commands and extended commands, a rich set of peripheral commands can be accommodated thereby further reducing or eliminating the need to provide different versions of software executing on the processor, while nevertheless exploiting the full capabilities of a wide variety of peripheral devices, including state of the art hardware devices such as bit-mapped displays, pointer devices and the like. Method and apparatus embodiments are described.

公开(公告)号：CA2476913A1

公开(公告)日：2003-09-04

申请号：CA2476913

申请日：2003-02-21

Applicant: QUALCOMM INC

Inventor： HUSSEINI JALAL ,  LI TAO ,  ARCEO JULIO ,  KANG INYUP ,  WEI JIAN ,  OISHI MOTO ,  RODRIGUES BRIAN ,  MEAGHER BRUCE ,  HIGGINS RICHARD

IPC: G06F11/10 ,  G06F3/06 ,  G06F7/00 ,  G06F12/00 ,  G06F12/06 ,  G06F12/16 ,  G06F13/16 ,  G06F13/28 ,  G11C7/00 ,  G11C7/10 ,  G11C14/00 ,  G11C16/04 ,  H04B7/00

Abstract: Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specifi c design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage unit s, and a data bus coupled to both storage units and the EMI unit. The two stora ge units are implemented external to the ASIC, and each storage unit is operabl e to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.

公开(公告)号：AU2609201A

公开(公告)日：2001-07-16

申请号：AU2609201

申请日：2000-12-29

Applicant: QUALCOMM INC

Inventor： LUDWIN ALBERT SCOTT ,  SHI GUANMING ,  HIGGINS RICHARD ,  BAYLEY GWAIN

IPC: G06F9/45 ,  G06F13/10 ,  H04B7/26

Abstract: The virtual device architecture provides physical and logical device drivers for interfacing software programs executing on a microprocessor of the mobile telephone of a wireless communication system with any of a wide variety of hardware devices connectable within the mobile telephone. The logical device drivers convert commands received from the software applications to commands appropriate for use by selected hardware devices. The physical device drivers receive the converted commands from the logical device drivers and in response to the received commands directly control the selected hardware devices. In one example described herein, the logical device drivers provide translation of core commands necessary to control the selected hardware devices and extended commands for enhanced control of the hardware devices. The logical device drivers operate to convert the extended commands into core commands prior to forwarding the commands to the physical device drivers. By providing logical and physical drivers for use with peripheral devices, the need to provide different versions of software executing on the microprocessor to accommodate different types of peripheral devices is substantially eliminated resulting in a considerable reduction in time and cost associated with developing, maintaining and upgrading software. By providing logical device drivers capable of accommodating both core commands and extended commands, a rich set of peripheral commands can be accommodated thereby further reducing or eliminating the need to provide different versions of software executing on the processor, while nevertheless exploiting the full capabilities of a wide variety of peripheral devices, including state of the art hardware devices such as bit-mapped displays, pointer devices and the like. Method and apparatus embodiments are described.

公开(公告)号：BRPI0509082A

公开(公告)日：2007-08-21

申请号：BRPI0509082

申请日：2005-03-11

Applicant: QUALCOMM INC

Inventor： SIH GILBERT CHRISTOPHER ,  SAKAMAKI CHARLES E ,  HSU DE D ,  WEI JIAN ,  HIGGINS RICHARD

IPC: G06F12/08

Abstract: A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.

公开(公告)号：AU2003213196A1

公开(公告)日：2003-09-09

申请号：AU2003213196

申请日：2003-02-21

Applicant: QUALCOMM INC

Inventor： ARCEO JULIO ,  HUSSEINI JALAL ,  LI TAO ,  MEAGHER BRUCE ,  HIGGINS RICHARD ,  OISHI MOTO ,  RODRIGUES BRIAN ,  WEI JIAN ,  KANG INYUP

IPC: G06F11/10 ,  G06F3/06 ,  G06F7/00 ,  G06F12/00 ,  G06F12/06 ,  G06F12/16 ,  G06F13/16 ,  G06F13/28 ,  G11C7/00 ,  G11C7/10 ,  G11C14/00 ,  G11C16/04 ,  H04B7/00

Abstract: Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage units, and a data bus coupled to both storage units and the EMI unit. The two storage units are implemented external to the ASIC, and each storage unit is operable to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.

公开(公告)号：WO2005101213A3

公开(公告)日：2006-01-26

申请号：PCT/US2005008373

申请日：2005-03-11

Applicant: QUALCOMM INC ,  SIH GILBERT CHRISTOPHER ,  SAKAMAKI CHARLES E ,  HSU DE D ,  WEI JIAN ,  HIGGINS RICHARD

Inventor： SIH GILBERT CHRISTOPHER ,  SAKAMAKI CHARLES E ,  HSU DE D ,  WEI JIAN ,  HIGGINS RICHARD

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/08 ,  G06F12/0857 ,  G06F12/0897 ,  G06F2212/251 ,  G06F2212/253

Abstract: A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.

Abstract translation: 描述了可以处理高速率输入数据并确保嵌入式DSP能够满足实时约束的高速缓存存储器系统。 缓存的存储器系统包括位于处理器核心附近的高速缓存存储器，处于下一较高存储器级别的片上存储器以及最高存储器级别的外部主存储器。 缓存控制器处理高速缓冲存储器和片上存储器之间的指令和数据的分页用于高速缓存未命中。 直接存储交换（DME）控制器处理片上存储器和外部存储器之间的用户控制的寻呼。 用户/程序员可以安排在处理器核心实际需要之前将处理器核心所需的指令和数据存储在片上存储器中。