公开(公告)号：JP2013152778A

公开(公告)日：2013-08-08

申请号：JP2013038892

申请日：2013-02-28

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： CHEN CHI-TOWN ,  KANG INYUP ,  VIRAPHOL CHAIYAKUL

IPC: G11C11/413

Abstract: PROBLEM TO BE SOLVED: To provide a memory architecture optimized for random matrix process capability.SOLUTION: The memory includes an N-dimension array of bit cells 300 and logic configured to address each bit cell using N-dimension addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines 320, and N bit lines 332, 334.

Abstract translation: 要解决的问题：提供针对随机矩阵处理能力优化的存储器架构。解决方案：存储器包括位单元300的N维阵列和配置为使用N维寻址（NDA）寻址每个位单元的逻辑，其中N 是至少两个，并且位单元阵列可由N个正交地址空间寻址。 N维可寻址存储器的每个位单元包括位存储元件，N字线320和N位线332,334。

公开(公告)号：JP2010282637A

公开(公告)日：2010-12-16

申请号：JP2010157075

申请日：2010-07-09

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： SIH GILBERT C ,  ZOU QUIZHEN ,  JHA SANJAY K ,  KANG INYUP ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI CHARLES E ,  KANTAK PRASHANT A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F13/16 ,  G06F15/78

CPC classification number: G06F12/0886 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3885 ,  G06F9/3893 ,  G06F15/7807

Abstract: PROBLEM TO BE SOLVED: To provide a digital signal processor which enhances performance and availability. SOLUTION: A DSP includes a set of three data buses over which data may be exchanged with a register bank 120 and three data memories 102, 103 and 104. The register bank 120 may be used that includes registers accessible by at least two processing units 128 and 130. An instruction fetch unit 156 may include that receives instructions of variable length stored in an instruction memory 152. The instruction memory 152 may be separated from the set of three data memories 102, 103 and 104. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种提高性能和可用性的数字信号处理器。 解决方案：DSP包括一组三条数据总线，数据可以通过该组三个数据总线与寄存器组120和三个数据存储器102,103和104进行交换。可以使用寄存器组120，其包括可由至少两个 处理单元128和130.指令提取单元156可以包括接收存储在指令存储器152中的可变长度的指令。指令存储器152可以与三组数据存储器102,103和104分离。 ：（C）2011，JPO＆INPIT

公开(公告)号：JP2008022569A

公开(公告)日：2008-01-31

申请号：JP2007212248

申请日：2007-08-16

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： KANG INYUP

IPC: H03M13/13 ,  H03M13/29 ,  H03M13/27 ,  H03M13/45 ,  H04L1/00 ,  H04L13/08

CPC classification number: H03M13/3905 ,  H03M13/2975 ,  H03M13/2984 ,  H03M13/6502 ,  H03M13/6505 ,  H03M13/6563

Abstract: PROBLEM TO BE SOLVED: To solve the problem that an efficient dealing method for eliminating the necessity to attach a memory bank is required.
SOLUTION: The disclosed turbo decoder includes a first mode of operation in which the turbo decoder uses a first functional loop. The first functional loop includes a memory bank, a read interleaver, a first multiplexer (MUX), a RAM file, a log-MAP decoder, a write interleaver, and a second MUX. The disclosed turbo decoder further includes a second mode of operation in which a second functional loop is used. The second functional loop includes the memory bank, the first MUX, the RAM file, the log-MAP decoder, and the second MUX. The memory bank is a dual port extrinsic memory. The disclosed turbo decoder circuit switches between the first mode and the second mode.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了解决用于消除附加存储体的必要性的有效的处理方法的问题。 解决方案：所公开的turbo解码器包括turbo解码器使用第一功能环路的第一操作模式。 第一功能循环包括存储体，读交织器，第一多路复用器（MUX），RAM文件，对数MAP解码器，写交织器和第二MUX。 所公开的turbo解码器还包括使用第二功能回路的第二操作模式。 第二功能循环包括存储体，第一MUX，RAM文件，log-MAP解码器和第二MUX。 存储器是双端口外部存储器。 所公开的turbo解码器电路在第一模式和第二模式之间切换。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：WO2006122101A2

公开(公告)日：2006-11-16

申请号：PCT/US2006017879

申请日：2006-05-08

Applicant: QUALCOMM INC ,  KANG INYUP

Inventor： KANG INYUP

IPC: H04B7/216

CPC classification number: H04B1/7083 ,  H04B1/70735

Abstract: A method and apparatus for reduced acquisition time are disclosed. In one embodiment, such as in a W-CDMA system, a receiver receives one or more signals from remote stations, each signal comprising a scrambling code associated with one of a plurality of code groups, each code group identified by a unique series of a synchronization codes. A searcher identifies a subset of first synchronization codes, and a processor selects one or more hypotheses in response to the received subset. The searcher may then perform searching for a scrambling code in accordance with the one or more hypotheses. The scrambling code search may be performed in parallel with continued synchronization code searching. Various other embodiments are also disclosed.

Abstract translation: 公开了一种缩短采集时间的方法和装置。 在一个实施例中，例如在W-CDMA系统中，接收机从远程站接收一个或多个信号，每个信号包括与多个代码组中的一个相关联的扰码，每个代码组由唯一的一系列 同步码 搜索者识别第一同步码的子集，并且处理器响应于所接收的子集选择一个或多个假设。 然后，搜索者可以根据一个或多个假设执行搜索扰码。 可以与继续的同步码搜索并行地执行扰码搜索。 还公开了各种其它实施例。

公开(公告)号：CA2723046C

公开(公告)日：2013-02-19

申请号：CA2723046

申请日：2002-02-15

Applicant: QUALCOMM INC

Inventor： LI TAO ,  HOLENSTEIN CHRISTIAN ,  KANG INYUP ,  WALKER BRETT C ,  PETERZELL PAUL E ,  CHALLA RAGHU ,  SEVERSON MATTHEW L ,  RAGHUPATHY ARUN ,  SIH GILBERT C

IPC: H03G1/00 ,  H04B1/16 ,  H03G3/00 ,  H03G3/20 ,  H03G3/30 ,  H04B1/30 ,  H04J13/00 ,  H04L27/22 ,  H04L27/38

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

公开(公告)号：CA2438333C

公开(公告)日：2011-11-01

申请号：CA2438333

申请日：2002-02-15

Applicant: QUALCOMM INC

Inventor： LI TAO ,  HOLENSTEIN CHRISTIAN ,  KANG INYUP ,  WALKER BRETT C ,  PETERZELL PAUL E ,  CHALLA RAGHU ,  SEVERSON MATTHEW L ,  RAGHUPATHY ARUN ,  SIH GILBERT CHRISTOPHER

IPC: H03G1/00 ,  H03G3/20 ,  H03F3/68 ,  H03G3/30 ,  H04L27/22 ,  H04L27/38

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

公开(公告)号：CA2324219C

公开(公告)日：2011-05-10

申请号：CA2324219

申请日：1999-03-04

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  ZOU QUIZHEN ,  JHA SANJAY K ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI CHARLES E ,  KANTAK PRASHANT A ,  KANG INYUP

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

公开(公告)号：BR0209743A

公开(公告)日：2006-01-17

申请号：BR0209743

申请日：2002-05-31

Applicant: QUALCOMM INC

Inventor： KANG INYUP ,  LI TAO

IPC: H04B1/7075 ,  H04B1/7077 ,  H04B1/707 ,  H04L7/04

Abstract: In a real-time mode, a clock signal of a searcher architecture is disabled between synchronization sequence bursts. In a sample storage or asynchronous mode, portions of stored signals do not belong to any hypothesis to be tested (e.g. portions that occur between synchronization signal bursts) are not loaded into the searcher delay chain.

公开(公告)号：CA2343218C

公开(公告)日：2006-01-03

申请号：CA2343218

申请日：1999-09-03

Applicant: QUALCOMM INC

Inventor： AGRAWAL AVNEESH ,  GARDNER WILLIAM ,  ZOU QIUZHEN ,  SIH GILBERT C ,  KANG INYUP

IPC: G01S19/30 ,  G01S1/00 ,  G01S1/04 ,  G01S5/00 ,  G01S5/14 ,  G01S19/23 ,  G01S19/24 ,  G01S19/25 ,  G01S19/29 ,  G01S19/37 ,  H04Q7/32 ,  H04Q7/34 ,  H04Q7/36 ,  H04Q7/38

Abstract: The present invention is a novel and improved method and apparatus for performing position location in wireless communications system. One embodiment comprises a method for performing position location i n a wireless communication system using a set of signals transmitted from a set of satellites including the steps of receiving signal samples, rotating an acquisition code by a first rotation amount yielding a rotated acquisition code, despreading said signal samples using rotated acquisition code yielding despread data, accumulating said despread data over a first duration yielding partially accumulated data , rotating said partially accumulated data by a second rotation amount yielding rotated data and accumulating said rotated data.

公开(公告)号：DE69919729T2

公开(公告)日：2005-09-29

申请号：DE69919729

申请日：1999-09-03

Applicant: QUALCOMM INC

Inventor： KANG INYUP ,  SIH C ,  ZOU QIUZHEN

IPC: G01S5/00 ,  G01S19/23 ,  G01S19/25 ,  G01S19/29 ,  G01S19/30 ,  H04Q7/34 ,  G01S5/14

Abstract: The present invention is a novel and improved method and apparatus for performing position location in wireless communications system. One embodiment of the invention comprises a method for performing position location comprising the steps of receiving signal samples, generating a coarse acquisition sequence, rotating the coarse acquisition sequence yielding a rotated coarse acquisition sequence, and applying the rotated coarse acquisition sequence to the signal samples at a set of time offsets yielding correlated output data.