公开(公告)号：JP2012178165A

公开(公告)日：2012-09-13

申请号：JP2012089195

申请日：2012-04-10

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： LUCIAN CODRESCU ,  WILLIAM C ANDERSON ,  SURESH VENKUMAHANTI ,  LOUIS ACHIELE GIANNINI ,  MANOGIKMER PILA ,  CHEN XUFENG

IPC: G06F11/28

CPC classification number: G06F11/362 ,  G06F11/3656

Abstract: PROBLEM TO BE SOLVED: To debug a core processor in association with a multi-threaded digital signal processor.SOLUTION: Writing a stuffing instruction in a debugging process registry and writing a stuffing command in a debugging process command register identify a predetermined thread of the multi-threaded digital signal processor to execute the stuffing instruction. An instruction stuffing process issues a debugging process control resume command during a predetermined execution stage on the predetermined thread, and instructs the core processor to execute the stuffing instruction during the debugging process. Here, the core processor is capable of executing the stuffed instruction in association with the core processor process and the debugging process.

Abstract translation: 要解决的问题：调试与多线程数字信号处理器相关联的核心处理器。 解决方案：在调试过程注册表中写入填充指令并在调试过程命令寄存器中写入填充命令来标识多线程数字信号处理器的预定线程以执行填充指令。 指令填充处理在预定线程的预定执行阶段发出调试过程控制恢复命令，并且指示核心处理器在调试过程中执行填充指令。 这里，核心处理器能够与核心处理器处理和调试过程相关联地执行填充指令。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2013050966A

公开(公告)日：2013-03-14

申请号：JP2012223443

申请日：2012-10-05

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： LUCIAN CODRESCU ,  WILLIAM C ANDERSON ,  SURESH VENKUMAHANTI ,  LOUIS ACHIELE GIANNINI ,  MANOGIKMER PILA ,  CHEN XUFENG

IPC: G06F11/28

CPC classification number: G06F1/3203 ,  G06F11/362 ,  G06F11/3656

Abstract: PROBLEM TO BE SOLVED: To control debugging operation during digital signal processor power transitions.SOLUTION: When a warm boot power-down sequence 220 begins, at point 228, a power collapse interrupt occurs, causing a kernel shutdown handler to operate. In response, the power collapse interrupt is disabled (230). At point 232, the ISDB_CORE_READY register reads 0 and the JTAG read/write returns an invalid status. If an ISDB configuration change is in progress, a core processor causes the power-down sequence to be canceled. If the configuration is not in progress, then the power-down sequence 220 saves the ISDB configuration register contents to memory. A warm boot flag marker is set. Then, the power-down sequence stops all threads and DSP is powered down.

Abstract translation: 要解决的问题：在数字信号处理器电源转换期间控制调试操作。 解决方案：当热引导断电序列220开始时，在点228，发生电源崩溃中断，导致内核关闭处理程序运行。 作为响应，电源崩溃中断被禁用（230）。 在点232，ISDB_CORE_READY寄存器读为0，JTAG读/写返回无效状态。 如果正在进行ISDB配置更改，则核心处理器将导致掉电序列被取消。 如果配置不在进行中，则断电序列220将ISDB配置寄存器内容保存到存储器。 设置热启动标志标记。 然后，掉电序列停止所有线程，DSP断电。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2013254508A

公开(公告)日：2013-12-19

申请号：JP2013151110

申请日：2013-07-19

Applicant: QUALCOMM INC

Inventor： LUCIAN CODRESCU ,  WILLIAM C ANDERSON ,  SURESH VENKUMAHANTI ,  LOUIS ACHIELE GIANNINI ,  MANOGIKMER PILA ,  CHEN XUFENG

IPC: G06F11/28

Abstract: PROBLEM TO BE SOLVED: To capture detailed information on an execution flow of a DSP in real time in a non-intrusive manner.SOLUTION: An ETM 232 monitors a DSP pipeline. Using this information, the ETM performs filtering/triggering and compression/packetization. The filtering and triggering operations are programmed by a user through a JTAG interface 84. DSP execution information is received by a compression/packetization unit 236, sent out of the ETM through a trace port, and fed into an off-chip or on-chip trace repository 240. A decompressor component 246 is a software component running on an ISDB 82, and takes a packet stream from the trace repository and, along with a program image, reconstructs an execution flow of the DSP, giving the user detailed visibility of the DSP pipeline.

公开(公告)号：JP2013058207A

公开(公告)日：2013-03-28

申请号：JP2012209762

申请日：2012-09-24

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： LUCIAN CODRESCU ,  WILLIAM C ANDERSON ,  SURESH VENKUMAHANTI ,  LOUIS ACHIELE GIANNINI ,  MANOGIKMER PILA ,  CHEN XUFENG

IPC: G06F11/28 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/3005 ,  G06F9/3009 ,  G06F9/3851 ,  G06F11/362

Abstract: PROBLEM TO BE SOLVED: To provide non-intrusive debugging to real-time behavior in a multi-threaded DSP.SOLUTION: An ISDB is enabled (132) for DSP operation. If a hardware breakpoint 134, a software breakpoint 136, an ETM breakpoint 140, a JTAG breakpoint 142, or an external breakpoint 144 exists, the process proceeds to debugging operation 138. ISTEP debugging 150 is performed if the ISTEP debugging is effective. Instruction stuffing operation 154 is performed if the instruction stuffing operation is effective. If a core DSP reset instruction has been generated by the debugging operation, a core DSP digital signal processor is reset (156).

Abstract translation: 要解决的问题：为多线程DSP中的实时行为提供非侵入式调试。 解决方案：使能ISDB（132）进行DSP操作。 如果存在硬件断点134，软件断点136，ETM断点140，JTAG断点142或外部断点144，则处理进行到调试操作138.如果ISTEP调试有效，则执行ISTEP调试150。 如果指示填充操作有效，则执行指令填充操作154。 如果通过调试操作生成了核心DSP复位指令，则核心DSP数字信号处理器被复位（156）。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2012089144A

公开(公告)日：2012-05-10

申请号：JP2011254030

申请日：2011-11-21

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： RAJEEV KRISHNAMURSI ,  CHRISTOPHER EDWARD KUBE ,  WILLIAM C ANDERSON

IPC: G06F7/523

CPC classification number: G06F7/5338 ,  G06F7/49994 ,  G06F7/5443

Abstract: PROBLEM TO BE SOLVED: To perform sign extension having high power efficiency in a booth multiplication method.SOLUTION: A technology for the design and use of a digital signal processor includes processing communication such as CDMA. Sign extension includes applying a sign bit to a booth multiplication tree and enables booth multiplication processing to execute a sign extension step. This further includes using the sign bit to store a correct sign of a partial product row determined in advance and extending the partial product row determined in advance of the booth multiplication tree by one element. This sign extension bit is placed in a carry-out column to extend a product of booth multiplication processing. Next, a method and a system form the final product from the booth multiplication tree by adding a carry-out value to the sign bit placed in a column determined in advance of the booth multiplication tree. This result efficiently extends sum component of the final product having a sign and performs zero-extension of the carry component of the final product.

Abstract translation: 要解决的问题：在展位乘法方法中执行具有高功率效率的符号扩展。 解决方案：用于设计和使用数字信号处理器的技术包括处理诸如CDMA的通信。 标志扩展包括对展位乘法树应用符号位，并使展位乘法处理能够执行符号扩展步骤。 这还包括使用符号位来存储预先确定的部分乘积行的正确符号，并将预乘乘树之前确定的部分乘积行扩展一个元素。 此符号扩展位被放置在进位列中以扩展展位乘法处理的乘积。 接下来，一种方法和系统从展位乘法树形成最终产品，通过向放置在展位乘积树之前确定的列中的符号位添加进位值。 该结果有效地扩展具有符号的最终产品的总和分量，并执行最终产品的进位分量的零扩展。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：BRPI0608750B1

公开(公告)日：2018-01-16

申请号：BRPI0608750

申请日：2006-03-28

Applicant: QUALCOMM INC

Inventor： ERICH PLONDKE ,  LUCIAN CODRESCU ,  MUHAMMAD AHMED ,  WILLIAM C ANDERSON

IPC: G06F9/38

Abstract: método e sistema para emitir e processar instruções superescalar e vliw misturadas. são descritas técnicas para processar transmissões em um sistema de comunicação (por exemplo, cdma). um método e um sistema para emitir e executar instruções de estrutura misturadas em um processador de sinais digitais de múltipla emissão que recebe, em uma listagem de instruções misturadas, uma pluralidade de instruções de processador de sinais digitais. a pluralidade de instruções de processador de sinais digitais inclui uma pluralidade de instruções executáveis em paralelo (por exemplo, instruções vliw ou pacotes de instruções) misturadas entre uma pluralidade de instruções executáveis em série (por exemplo, instruções superescalares) . as instruções executáveis em série estão associadas por meio de várias dependências de instruções. o método e o sistema adicionalmente identificam na listagem de instruções misturadas a pluralidade de instruções executáveis em paralelo. uma vez identificadas, as instruções executáveis em paralelo são inicialmente executadas em paralelo desprezando-se qualquer ordem relativa de tais instruções na listagem de instruções misturadas. então, as instruções executáveis em série são executadas serialmente de acordo com as várias dependências de instruções.