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    INTEGRATED CIRCUIT (IC) PACKAGE AND PACKAGE SUBSTRATE COMPRISING STACKED VIAS
    1.
    发明申请
    INTEGRATED CIRCUIT (IC) PACKAGE AND PACKAGE SUBSTRATE COMPRISING STACKED VIAS 审中-公开

    公开(公告)号：WO2018204115A1

    公开(公告)日：2018-11-08

    申请号：PCT/US2018/028903

    申请日：2018-04-23

    Applicant: QUALCOMM INCORPORATED

    Inventor： KANG, Kuiwon ,  JOMAA, Houssam ,  ROUHANA, Layal ,  CHOI, Seongryul

    IPC: H01L23/498 ,  H01L21/48

    Abstract: A device comprising a semiconductor die, a package substrate coupled to the semiconductor die, and an encapsulation layer that at least partially encapsulates the semiconductor die. The package substrate includes at least one stacked via. The at least one stacked via includes a first via and a second via coupled to the first via. The second via includes a seed layer coupled to the first via. The second via includes a different shape than the first via. The package substrate includes a prepreg layer. The package substrate includes a first pad coupled to the first via, and a second pad coupled to the second via.

    ELECTRODELESS PASSIVE EMBEDDED SUBSTRATE
    2.
    发明申请
    ELECTRODELESS PASSIVE EMBEDDED SUBSTRATE 审中-公开

    公开(公告)号：WO2021035233A1

    公开(公告)日：2021-02-25

    申请号：PCT/US2020/070266

    申请日：2020-07-14

    Applicant: QUALCOMM INCORPORATED

    Inventor： KANG, Kuiwon ,  CHOI, Seongryul ,  KIM, Haekyun

    IPC: H01L25/16 ,  H01L23/498 ,  H01L21/98

    Abstract: An electronic assembly is disclosed that includes an electrodeless passive component (220) embedded in a cavity of a multilayer substrate (210), wherein the cavity (218) has conductive elements (214) formed on at least two sidewalls of the cavity. The conductive elements are configured to be electrically coupled to the electrodeless passive component. The electrodeless passive component may be located in a first metal layer adjacent an external surface of the multilayer substrate.

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