公开(公告)号：EP3254309A1

公开(公告)日：2017-12-13

申请号：EP16704361.1

申请日：2016-02-03

Applicant: Qualcomm Incorporated

Inventor： KIDWELL, Donald William, Jr. ,  SHENOY, Ravindra ,  ERTURK, Mete ,  ROUHANA, Layal

IPC: H01L23/498 ,  H01F17/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  B23K26/0661 ,  H01F17/0033 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/585 ,  H01L28/10 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: An integrated device package includes a die and a package substrate. The package substrate includes at least one dielectric layer (e.g., core layer, prepeg layer), a magnetic core in the dielectric layer, a first plurality of interconnects configured to operate as a first protective ring, and a second plurality of interconnects configured to operate as a first inductor. The second plurality of interconnects is positioned in the package substrate to at least partially surround the magnetic core. At least one interconnect from the second plurality of interconnects is also part of the first plurality of interconnects. In some implementations, the first protective ring is a non-contiguous protective ring. In some implementations, the first inductor is a solenoid inductor. In some implementations, the magnetic core includes a carrier, a first magnetic layer, and a second magnetic layer.

公开(公告)号：WO2018204115A1

公开(公告)日：2018-11-08

申请号：PCT/US2018/028903

申请日：2018-04-23

Applicant: QUALCOMM INCORPORATED

Inventor： KANG, Kuiwon ,  JOMAA, Houssam ,  ROUHANA, Layal ,  CHOI, Seongryul

IPC: H01L23/498 ,  H01L21/48

Abstract: A device comprising a semiconductor die, a package substrate coupled to the semiconductor die, and an encapsulation layer that at least partially encapsulates the semiconductor die. The package substrate includes at least one stacked via. The at least one stacked via includes a first via and a second via coupled to the first via. The second via includes a seed layer coupled to the first via. The second via includes a different shape than the first via. The package substrate includes a prepreg layer. The package substrate includes a first pad coupled to the first via, and a second pad coupled to the second via.

公开(公告)号：WO2018175099A1

公开(公告)日：2018-09-27

申请号：PCT/US2018/020918

申请日：2018-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： KANG, Kuiwon ,  JOMAA, Houssam ,  BAHR, Christopher ,  ROUHANA, Layal

IPC: H01L23/538

Abstract: A package that includes a substrate comprising an interposer interconnect and a cavity, a redistribution portion coupled to the substrate, the redistribution comprising a plurality of redistribution interconnects, and a first die coupled to the redistribution portion through the cavity of the substrate. A substantial region between a side surface of the first die and the substrate is free of an encapsulation layer. In some implementations, the substrate is free of a metal ring that surrounds the first die. In some implementations, the redistribution portion comprises a barrier layer and a first interconnect coupled to the barrier layer. The barrier layer is coupled to the interposer interconnect.

公开(公告)号：WO2016126881A1

公开(公告)日：2016-08-11

申请号：PCT/US2016/016458

申请日：2016-02-03

Applicant: QUALCOMM INCORPORATED

Inventor： KIDWELL, Donald William, Jr. ,  SHENOY, Ravindra ,  ERTURK, Mete ,  ROUHANA, Layal

IPC: H01L23/498 ,  H01F17/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  B23K26/0661 ,  H01F17/0033 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/585 ,  H01L28/10 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: An integrated device package includes a die and a package substrate. The package substrate includes at least one dielectric layer (e.g., core layer, prepeg layer), a magnetic core in the dielectric layer, a first plurality of interconnects configured to operate as a first protective ring, and a second plurality of interconnects configured to operate as a first inductor. The second plurality of interconnects is positioned in the package substrate to at least partially surround the magnetic core. At least one interconnect from the second plurality of interconnects is also part of the first plurality of interconnects. In some implementations, the first protective ring is a non-contiguous protective ring. In some implementations, the first inductor is a solenoid inductor. In some implementations, the magnetic core includes a carrier, a first magnetic layer, and a second magnetic layer.

Abstract translation: 集成器件封装包括管芯和封装衬底。 封装衬底包括至少一个电介质层（例如芯层，预镀层），电介质层中的磁芯，被配置为作为第一保护环工作的第一多个互连件和被构造成操作的第二多个互连件 作为第一电感器。 所述第二多个互连件定位在所述封装衬底中以至少部分地围绕所述磁芯。 来自第二多个互连的至少一个互连也是第一多个互连的一部分。 在一些实施方案中，第一保护环是不连续的保护环。 在一些实施方式中，第一电感器是螺线管电感器。 在一些实施方案中，磁芯包括载体，第一磁性层和第二磁性层。

公开(公告)号：WO2016100829A2

公开(公告)日：2016-06-23

申请号：PCT/US2015/066698

申请日：2015-12-18

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Young Kyu ,  ROUHANA, Layal ,  HWANG, Kyu-Pyung ,  BCHIR, Omar James

IPC: H05K1/02 ,  H05K1/16

CPC classification number: H05K3/4644 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/0234 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/167 ,  H05K1/181 ,  H05K3/1258 ,  H05K3/321 ,  H05K3/3442 ,  H05K3/4697 ,  H05K2201/0792 ,  H05K2201/09227 ,  H05K2201/09281 ,  H05K2201/09954 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2203/0545 ,  Y02P70/611

Abstract: Methods and apparatus for controlling an equivalent-series resistance (ESR) of a capacitor are provided. An exemplary apparatus includes a substrate having a land side, the capacitor mounted on the land side of the substrate and having both the ESR and terminals, a resistive pattern coupled to the terminals, and a plurality of vias coupled to the resistive pattern. The resistive pattern is configured to control the ESR. The resistive pattern can be formed of a resistive paste. The resistive pattern can be formed in a substantially semicircular shape having an arc ranging from substantially 45 degrees to substantially 135 degrees. The capacitor can be a surface mount device. The resistive pattern can be formed in a shape of a land-side capacitor mounting pad, a via, or both.

Abstract translation: 提供了用于控制电容器的等效串联电阻（ESR）的方法和装置。 示例性装置包括具有接地侧的基板，安装在基板的接地侧上并具有ESR和端子的电容器，耦合到端子的电阻图案以及耦合到电阻图案的多个通孔。 电阻模式被配置为控制ESR。 电阻图案可以由电阻浆料形成。 电阻图案可以形成为具有大致45度至基本上135度的弧度的大致半圆形状。 电容器可以是表面贴装器件。 电阻图案可以形成为陆侧电容器安装垫，通孔或两者的形状。

公开(公告)号：WO2019045892A1

公开(公告)日：2019-03-07

申请号：PCT/US2018/042360

申请日：2018-07-17

Applicant: QUALCOMM INCORPORATED

Inventor： KANG, Kuiwon ,  JOMAA, Houssam ,  ROUHANA, Layal

IPC: H01L23/498

Abstract: Some features pertain to a substrate that includes a first dielectric, a first interconnect, and a second interconnect. The first interconnect is at least partially embedded in the first dielectric layer. The first interconnect includes a first portion and a second portion. The first portion is configured to increase reliability as compared to a substrate having only a second portion of a first interconnect. The increase in reliability due at least in part to the first portion providing additional interconnect material to mitigate interconnect material lost through electromigration. A part of the second portion (of the first interconnect) is free of the first dielectric and may be configured to be coupled to another device.

公开(公告)号：WO2016049433A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/052184

申请日：2015-09-25

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Chin-Kwan ,  KUMAR, Rajneesh ,  ROUHANA, Layal ,  BUOT, Joan Rey V. ,  BCHIR, Omar James

IPC: H01L23/498 ,  H01L23/538

CPC classification number: H01L23/5226 ,  H01L21/76834 ,  H01L21/76898 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5389 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15333 ,  H01L2924/19041 ,  H01L2924/19106

Abstract: A semiconductor substrate according to some examples of the disclosure may include a substrate with a cavity in a top surface of the substrate, a plurality of cavity interconnections embedded below a bottom surface of the cavity and extending to a bottom surface of the substrate, and a plurality of side interconnections to either side of the cavity extending from the top surface of the substrate to the bottom surface of the substrate. Each of the plurality of side interconnections may include an electrically conductive stop etch layer in the same horizontal plane as the bottom of the cavity.

Abstract translation: 根据本公开的一些示例的半导体衬底可以包括在衬底的顶表面中具有空腔的衬底，多个腔互连嵌入在腔的底表面下方并延伸到衬底的底表面，并且 多个侧面互连到空腔的任一侧，从基板的顶表面延伸到基板的底表面。 多个侧面互连中的每一个可以包括在与空腔的底部相同的水平平面中的导电停止蚀刻层。

公开(公告)号：WO2016018950A1

公开(公告)日：2016-02-04

申请号：PCT/US2015/042542

申请日：2015-07-28

Applicant: QUALCOMM INCORPORATED

Inventor： KUMAR, Rajneesh ,  JOMAA, Houssam Wafic ,  RAE, David Fraser ,  ROUHANA, Layal ,  BCHIR, Omar James

IPC: H01L23/498

CPC classification number: H01L21/76852 ,  H01L21/4825 ,  H01L21/76879 ,  H01L23/4952 ,  H01L23/49527 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/53204 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/00014

Abstract: Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.

Abstract translation: 一些特征涉及集成器件，其包括第一衬底，耦合到第一衬底的第一阻焊层，耦合到第一阻焊层的第二阻焊层，以及第一和第二阻焊层中的开口， 开口，其包括完全被第二阻焊层覆盖的侧壁，其中第二阻焊层的侧壁覆盖第一阻焊层的侧壁。 在一些实施方案中，开口至少部分地填充有导电材料。 导电材料包括焊料和/或互连中的一种。 集成器件包括耦合到导电材料的第一互连。 第一互连是至少焊料和/或互连球之一。 在一些实施方案中，集成器件包括耦合到衬底的焊盘和耦合到焊盘的第一互连。