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    PACKAGE SUBSTRATE WITH TESTING PADS ON FINE PITCH TRACES
    1.
    发明申请
    PACKAGE SUBSTRATE WITH TESTING PADS ON FINE PITCH TRACES 审中-公开
    包装衬底，带有测试垫

    公开(公告)号：WO2014134059A2

    公开(公告)日：2014-09-04

    申请号：PCT/US2014/018372

    申请日：2014-02-25

    Applicant: QUALCOMM INCORPORATED

    Inventor： KIM, Chin-Kwan ,  KANG, Kuiwon ,  BCHIR, Omar J.

    IPC: H05K1/02

    CPC classification number: H05K1/111 ,  G01R31/2818 ,  H05K1/0268 ,  H05K3/3452 ,  H05K2201/10674 ,  Y10T29/49004 ,  Y10T29/49124 ,  Y10T29/4913

    Abstract: Some implementations provide a substrate that includes several traces, a solder resist layer covering the several traces, and a testing pad coupled to a trace from the several traces. The testing pad is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate. In some implementations, the several traces have a pitch that is 100 microns (m) or less. In some implementations, the substrate is a package substrate. In some implementations, the package substrate is a package substrate on which a thermal compression flip chip is mounted during an assembly process. In some implementations, the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate. In some implementations, the bonding component is one of a solder ball.

    Abstract translation: 一些实施方案提供了包括几条迹线的衬底，覆盖几条迹线的阻焊层，以及耦合到几条迹线的迹线的测试焊盘。 当芯片耦合到衬底时，测试焊盘至少部分地暴露并且至少部分地不含阻焊层。 在一些实施方案中，多个迹线具有100微米（m）或更小的间距。 在一些实施方式中，衬底是封装衬底。 在一些实施方案中，封装衬底是在组装过程期间安装热压缩倒装芯片的封装衬底。 在一些实施方案中，当芯片耦合到衬底时，测试焊盘不与芯片的焊接部件直接连接。 在一些实施方式中，接合部件是焊球之一。

    PACKAGE WITH A SUBSTRATE COMPRISING PROTRUDING PAD INTERCONNECTS
    2.
    发明申请
    PACKAGE WITH A SUBSTRATE COMPRISING PROTRUDING PAD INTERCONNECTS 审中-公开

    公开(公告)号：WO2022251342A1

    公开(公告)日：2022-12-01

    申请号：PCT/US2022/030899

    申请日：2022-05-25

    Applicant: QUALCOMM INCORPORATED

    Inventor： KANG, Kuiwon ,  WE, Hong Bok ,  KIM, Chin-Kwan ,  SHAH, Milind

    IPC: H01L23/498

    Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a plurality of protruding pad interconnects, and a solder resist layer located over the at least one dielectric layer, the solder resist layer comprising a thickness that is greater than a thickness of the plurality of protruding pad interconnects. A protruding pad interconnect may include a first pad portion and a second pad portion.

    INTEGRATED CIRCUIT (IC) PACKAGE SUBSTRATE WITH EMBEDDED TRACE SUBSTRATE (ETS) LAYER ON A SUBSTRATE, AND RELATED FABRICATION METHODS
    3.
    发明申请
    INTEGRATED CIRCUIT (IC) PACKAGE SUBSTRATE WITH EMBEDDED TRACE SUBSTRATE (ETS) LAYER ON A SUBSTRATE, AND RELATED FABRICATION METHODS 审中-公开

    公开(公告)号：WO2022046511A1

    公开(公告)日：2022-03-03

    申请号：PCT/US2021/046686

    申请日：2021-08-19

    Applicant: QUALCOMM INCORPORATED

    Inventor： KANG, Kuiwon ,  KIM, Chin-Kwan ,  PARK, Joonsuk

    IPC: H01L21/48 ,  H01L23/498 ,  H01L23/538

    Abstract: Integrated circuit (IC) package substrate with an embedded trace substrate (ETS) layer on a substrate, and related fabrication methods. The package substrate of the IC package includes an ETS layer provided on the substrate to facilitate providing higher density substrate interconnects to provide bump/solder joints for coupling a semiconductor die to the package substrate. ETS interconnects in the ETS layer in the package substrate facilitates die connections having a reduced line-spacing ratio (L/S) (e.g., 5.0 micrometers (µm)/5.0 µm or less) over substrate interconnects in a substrate. In additional exemplary aspects, raised metal pillar interconnects are formed in contact with respective ETS interconnects of the ETS layer of the package substrate to avoid or reduce metal consumption by die solder disposed on metal pillar interconnects of the ETS layer providing bump/solder joints.

    MULTICORE SUBSTRATE
    5.
    发明申请
    MULTICORE SUBSTRATE 审中-公开

    公开(公告)号：WO2021243195A1

    公开(公告)日：2021-12-02

    申请号：PCT/US2021/034826

    申请日：2021-05-28

    Applicant: QUALCOMM INCORPORATED

    Inventor： BUOT, Joan Rey Villarba ,  WANG, Zhijie ,  PATIL, Aniket ,  WE, Hong Bok ,  KANG, Kuiwon

    IPC: H01L23/498

    Abstract: Various package configurations and methods of fabricating the same are disclosed. In some aspects, a package may include a core layer and a first layer directly attached to a first side of the core layer, where a first device is embedded in the first layer. A second layer can be directly attached to a second side of the core layer opposite the first side, where a second passive device is embedded in the second layer. A first build-up layer can be directly attached to the first layer opposite the core layer, and a second build-up layer can be directly attached to the second layer opposite the core layer.

    INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING A THERMAL CONDUCTIVE PACKAGE SUBSTRATE WITH DIE REGION SPLIT, AND RELATED FABRICATION METHODS
    6.
    发明申请
    INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING A THERMAL CONDUCTIVE PACKAGE SUBSTRATE WITH DIE REGION SPLIT, AND RELATED FABRICATION METHODS 审中-公开

    公开(公告)号：WO2021158282A1

    公开(公告)日：2021-08-12

    申请号：PCT/US2020/063935

    申请日：2020-12-09

    Applicant: QUALCOMM INCORPORATED

    Inventor： KANG, Kuiwon ,  PATIL, Aniket ,  YAN, Bohan ,  HE, Dongming

    IPC: H01L23/367

    Abstract: Integrated circuit (IC) packages employing a thermal conductive semiconductor package substrate with die region split and related fabrication methods are disclosed. The package substrate includes a die split where metal contacts in one or more dielectric layers of the package substrate underneath the IC die(s) are thicker (e.g., in a core die region) than other metal contacts (e.g., in a peripheral die region) in the dielectric layer. This facilitates higher thermal dissipation from the IC die(s) through the thicker metal contacts in the package substrate. Cross-talk shielding of the package substrate may not be sacrificed since thinner metal contacts of the package substrate that carry high speed signaling can be of lesser thickness than the thicker metal contacts that provide higher thermal dissipation. The dielectric layer in the package substrate may also include dielectric materials having different thermal conductivities to further facilitate thermal dissipation and/or desired electrical or mechanical characteristics.

    HIGH DENSITY INTERCONNECTS IN AN EMBEDDED TRACE SUBSTRATE (ETS) COMPRISING A CORE LAYER
    7.
    发明申请
    HIGH DENSITY INTERCONNECTS IN AN EMBEDDED TRACE SUBSTRATE (ETS) COMPRISING A CORE LAYER 审中-公开

    公开(公告)号：WO2020009827A1

    公开(公告)日：2020-01-09

    申请号：PCT/US2019/038734

    申请日：2019-06-24

    Applicant: QUALCOMM INCORPORATED

    Inventor： KANG, Kuiwon ,  JOMAA, Houssam

    IPC: H01L21/48 ,  H01L23/498

    Abstract: A substrate that includes a first substrate portion, a second substrate portion and a second dielectric layer. The first substrate portion includes a core layer having a first core surface, and a plurality of core substrate interconnects, wherein the plurality of core substrate interconnects includes a plurality of surface core substrate interconnects formed over the first surface of core layer. The second substrate portion includes a first dielectric layer having a first dielectric surface, the first dielectric surface facing the first core surface of the core layer, and a plurality of substrate interconnects, wherein the plurality of substrate interconnects includes a plurality of interconnects formed over the first dielectric surface. The second dielectric layer is formed between the first substrate portion and the second substrate portion such that the plurality of surface core substrate interconnects and the plurality of substrate interconnects are located in the second dielectric layer.

    SUBSTRATE AND METHOD OF FORMING THE SAME
    8.
    发明申请
    SUBSTRATE AND METHOD OF FORMING THE SAME 审中-公开
    基板及其形成方法

    公开(公告)号：WO2015175197A1

    公开(公告)日：2015-11-19

    申请号：PCT/US2015/027806

    申请日：2015-04-27

    Applicant: QUALCOMM INCORPORATED

    Inventor： JOMAA, Houssam Wafic ,  BCHIR, Omar James ,  KANG, Kuiwon ,  KIM, Chin-Kwan

    IPC: H01L21/48 ,  H01L23/538 ,  H01L21/683

    CPC classification number: H01L23/5226 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods and apparatus for formation of a semiconductor substrate with photoactive dielectric material, embedded traces, a padless skip via extending through two dielectric layers, and a coreless package are provided. In one embodiment, a method for forming a core having a copper layer; laminating the copper layer a photoactive dielectric layer; forming a plurality of trace patterns in the photoactive dielectric layer; plating the plurality of trace patterns to form a plurality of traces; forming an insulating dielectric layer on the photoactive dielectric layer; forming a via through the insulating dielectric layer and the photoactive dielectric layer; forming additional routing patterns on the insulating dielectric layer; removing the core; and applying a solder mask.

    Abstract translation: 提供了用光电介质材料形成半导体衬底的方法和装置，嵌入迹线，延伸穿过两个电介质层的无衬垫跳过和无芯封装。 在一个实施例中，一种形成具有铜层的芯的方法; 将铜层层压成光电介质层; 在光电介质层中形成多个迹线图案; 电镀所述多个迹线图案以形成多个迹线; 在光电介质层上形成绝缘介电层; 通过所述绝缘介电层和所述光电介质层形成通孔; 在所述绝缘介电层上形成额外的布线图案; 去除核心; 并施加焊接掩模。

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