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    DOWNLINK CONTROL AND RETRANSMISSION INDICATOR CHANNEL FOR RELAXING ACK PROCESSING TIME CONSTRAINTS
    2.
    发明申请
    DOWNLINK CONTROL AND RETRANSMISSION INDICATOR CHANNEL FOR RELAXING ACK PROCESSING TIME CONSTRAINTS 审中-公开
    下行链路控制和重传指示信道用于放宽ACK处理时间约束

    公开(公告)号：WO2017160473A1

    公开(公告)日：2017-09-21

    申请号：PCT/US2017/018515

    申请日：2017-02-17

    Applicant: QUALCOMM INCORPORATED

    Inventor： ANG, Peter Pui Lok ,  JIANG, Jing ,  MUKKAVILLI, Krishna Kiran ,  JI, Tingfang ,  SMEE, John Edward ,  LIN, Jamie Menjay ,  COOPER, Rotem ,  HOWARD, Michael Alexander

    IPC: H04L1/18 ,  H04L1/00

    Abstract: Systems and methods are disclosed for minimizing latency between receipt of a NACK at a base station from a user equipment (UE) and retransmission of data to the UE. Time constraints for processing the ACK/NACK are relaxed so the base station can decode the ACK/NACK to determine whether a NACK has been received and then prepare for transmission of the appropriate data to the UE in the immediately following transmission time interval (TTI). These constraints are relaxed by separating download data indicator (DDI) from the PDCCH control data and delaying transmission of the DDI until decoding of the ACK/NACK.

    Abstract translation: 公开了用于最小化从基站接收到来自用户设备（UE）的NACK与向UE重传数据之间的等待时间的系统和方法。 用于处理ACK / NACK的时间约束被放宽，使得基站可以解码ACK / NACK以确定是否已经接收到NACK，并且然后准备在紧接的传输时间间隔（TTI）中向UE发送适当的数据， 。 通过从PDCCH控制数据分离下载数据指示符（DDI）并延迟DDI的传输直到ACK / NACK解码，放宽这些约束。

    APPARATUS AND METHOD FOR SYNCHRONOUS MULTIPLEXING AND MULTIPLE ACCESS FOR DIFFERENT LATENCY TARGETS UTILIZING THIN CONTROL
    4.
    发明申请
    APPARATUS AND METHOD FOR SYNCHRONOUS MULTIPLEXING AND MULTIPLE ACCESS FOR DIFFERENT LATENCY TARGETS UTILIZING THIN CONTROL 审中-公开
    用于利用薄控制的不同延迟目标的同步多路复用和多路访问的装置和方法

    公开(公告)号：WO2015179136A1

    公开(公告)日：2015-11-26

    申请号：PCT/US2015/029649

    申请日：2015-05-07

    Applicant: QUALCOMM INCORPORATED

    Inventor： JI, Tingfang ,  SMEE, John Edward ,  SORIAGA, Joseph Binamira ,  BHUSHAN, Naga ,  GAAL, Peter ,  GOROKHOV, Alexei Yurievitch ,  MUKKAVILLI, Krishna Kiran ,  HOWARD, Michael Alexander ,  COOPER, Rotem ,  ANG, Peter

    IPC: H04W72/12

    CPC classification number: H04W72/1231 ,  H04W56/002 ,  H04W72/042 ,  H04W72/1247 ,  H04W72/1278

    Abstract: Aspects of the disclosure provide for a thin control channel structure that can be utilized to enable multiplexing of two or more data transmission formats. For example, a thin control channel may carry information that enables ongoing transmissions utilizing a first, relatively long transmission time interval (TTI) to be punctured, and during the punctured portion of the long TTI, a transmission utilizing a second, relatively short TTI may be inserted. This puncturing is enabled by virtue of a thin channel structure wherein a control channel can carry scheduling information, grants, etc., informing receiving devices of the puncturing that is occurring or will occur. Furthermore, the thin control channel can be utilized to carry other control information, not being limited to puncturing information. Other aspects, embodiments, and features are also claimed and described.

    Abstract translation: 本公开的各方面提供了可用于实现两种或更多种数据传输格式的复用的薄控制信道结构。 例如，精简控制信道可携带使得能够利用第一较长传输时间间隔（TTI）进行正在进行的传输的信息被删截，并且在长TTI的删余部分期间，利用第二相对较短的TTI的传输可以 被插入。 该打孔通过细通道结构实现，其中控制通道可以携带调度信息，授权等，以通知接收设备正在发生或将要发生的打孔。 此外，可以利用细控制信道来传送其他控制信息，而不限于打孔信息。 其他方面，实施例和特征也被要求和描述。

    PACKET-BASED PROCESSING SYSTEM
    5.
    发明申请
    PACKET-BASED PROCESSING SYSTEM 审中-公开
    基于分组的处理系统

    公开(公告)号：WO2009026554A2

    公开(公告)日：2009-02-26

    申请号：PCT/US2008/074091

    申请日：2008-08-22

    Applicant: QUALCOMM INCORPORATED ,  IRANINEJAD, Mehraban ,  LEVIN, Jeffrey A. ,  CANOY, Michael-david N. ,  HOWARD, Michael Alexander ,  ZIV, Noam A. ,  SALVI, Rohan Sudhakar

    Inventor： IRANINEJAD, Mehraban ,  LEVIN, Jeffrey A. ,  CANOY, Michael-david N. ,  HOWARD, Michael Alexander ,  ZIV, Noam A. ,  SALVI, Rohan Sudhakar

    CPC classification number: H04W24/02 ,  H04L49/90 ,  H04L69/22 ,  H04W88/02 ,  H04W88/08

    Abstract: A packet-based processing system suitable for various applications, such as for a base station or a terminal in a wireless communication system, is described. The packet-based processing system may include multiple processing modules and at least one transport module. The processing modules may send packets to one another via a common packet interface and may operate asynchronously. The transport module(s) may forward the packets sent by the processing modules and may operate asynchronously with respect to the processing modules. Each processing module may include a network interface, at least one buffer, a packet parser, a packet builder, and at least one processing unit. Each processing module may support at least one service. Each packet may include a header and a payload. The header may include a source service address for a source service sending the packet and a destination service address for a recipient service receiving the packet.

    Abstract translation: 描述适用于各种应用的基于分组的处理系统，例如用于无线通信系统中的基站或终端的分组处理系统。 基于分组的处理系统可以包括多个处理模块和至少一个传输模块。 处理模块可以经由公共分组接口将分组发送到彼此并且可以异步操作。 传输模块可以转发由处理模块发送的分组并且可以相对于处理模块异步地操作。 每个处理模块可以包括网络接口，至少一个缓冲器，分组分析器，分组构建器以及至少一个处理单元。 每个处理模块可以支持至少一个服务。 每个数据包可能包含一个头和一个有效载荷。 报头可以包括发送分组的源服务的源服务地址和接收分组的接收服务的目的地服务地址。

    SCALABLE SCHEDULER ARCHITECTURE FOR CHANNEL DECODING
    8.
    发明申请
    SCALABLE SCHEDULER ARCHITECTURE FOR CHANNEL DECODING 审中-公开
    用于信道解码的可调度调度器架构

    公开(公告)号：WO2011143305A1

    公开(公告)日：2011-11-17

    申请号：PCT/US2011/036059

    申请日：2011-05-11

    Applicant: QUALCOMM Incorporated ,  CHANG, Wei-Hsin ,  PAN, Hanfang ,  HOWARD, Michael Alexander ,  WU, Wenqing ,  FUCHS, Robert Jason

    Inventor： CHANG, Wei-Hsin ,  PAN, Hanfang ,  HOWARD, Michael Alexander ,  WU, Wenqing ,  FUCHS, Robert Jason

    IPC: H04L1/00

    CPC classification number: H04L1/0052

    Abstract: Certain aspects of the present disclosure relate to a method for processing wireless communications. According to one aspect, a processing unit may receive a plurality of code blocks of a transport block and schedule the plurality of code blocks to be decoded in parallel with a plurality of decoders. Each decoder decodes at least one code block as an independent tasks. The processing unit further collects the decoded information bits from the plurality of decoders and forwards the collected decoded information bits for further processing. In one aspect, the processing unit includes an output agent to temporarily store the decoded information bits while waiting for all code blocks of the transport block to be decoded.

    Abstract translation: 本公开的某些方面涉及一种用于处理无线通信的方法。 根据一个方面，处理单元可以接收传输块的多个码块，并且与多个解码器并行地调度要解码的多个码块。 至少一个解码器解码至少一个代码块作为独立任务。 处理单元进一步从多个解码器中收集解码的信息比特，并且转发所收集的解码信息比特用于进一步处理。 一方面，处理单元包括一个输出代理，用于临时存储解码的信息位，同时等待传输块的所有代码块被解码。

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