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    UNIDIRECTIONAL CLOCK SIGNALING IN A HIGH-SPEED SERIAL LINK
    1.
    发明申请
    UNIDIRECTIONAL CLOCK SIGNALING IN A HIGH-SPEED SERIAL LINK 审中-公开
    高速串行链路中的单向时钟信号

    公开(公告)号：WO2017136474A1

    公开(公告)日：2017-08-10

    申请号：PCT/US2017/016092

    申请日：2017-02-01

    Applicant: QUALCOMM INCORPORATED

    Inventor： KHAN, Raheel ,  CHENG, Scott ,  PHILIPPE, Pascal ,  ROMERA, Joaquin

    IPC: H04L7/00 ,  G06F13/42 ,  H04B1/40

    CPC classification number: G06F13/4291 ,  G06F9/00 ,  G06F13/364 ,  H04B1/40 ,  H04L7/0008 ,  H04L7/046 ,  H04L29/06 ,  H04L67/2823 ,  H04L69/00 ,  H04L69/22

    Abstract: Transmission of data over a serial link based on a unidirectional clock signal is provided. A unidirectional clock signal is generated based on a first clock of a master device. The unidirectional clock signal is sent to a slave device that is connected to the serial link. The master device transmits data to the slave device over the serial link based on the first clock. The slave device receives the unidirectional clock signal from a master device. The slave device transmits data over the serial link to the master device based on the unidirectional clock signal.

    Abstract translation: 提供基于单向时钟信号通过串行链路传输数据。 基于主设备的第一时钟生成单向时钟信号。 单向时钟信号被发送到连接到串行链路的从设备。 主设备基于第一时钟通过串行链路将数据发送到从设备。 从设备接收来自主设备的单向时钟信号。 从设备根据单向时钟信号通过串行链路将数据传输到主设备。

    SCALABLE, HIGH-EFFICIENCY, HIGH-SPEED SERIALIZED INTERCONNECT
    2.
    发明申请
    SCALABLE, HIGH-EFFICIENCY, HIGH-SPEED SERIALIZED INTERCONNECT 审中-公开
    可扩展，高效率，高速串行互连

    公开(公告)号：WO2017136455A1

    公开(公告)日：2017-08-10

    申请号：PCT/US2017/016071

    申请日：2017-02-01

    Applicant: QUALCOMM INCORPORATED

    Inventor： KHAN, Raheel ,  CHENG, Scott ,  PHILIPPE, Pascal ,  ROMERA, Joaquin

    IPC: H04L29/06

    CPC classification number: G06F13/4291 ,  G06F9/00 ,  G06F13/364 ,  H04B1/40 ,  H04L7/0008 ,  H04L7/046 ,  H04L29/06 ,  H04L67/2823 ,  H04L69/00 ,  H04L69/22

    Abstract: Serial communication using a packetization protocol engineered for efficient transmission is provided. Data link layer (DLL) control packets can be generated for transmission of control messages. Each DLL control message packet can have a DLL control packet length, and the DLL control packet length can be a fixed length. Physical layer (PHY) control packets can be generated. Each PHY control packet can include one of the DLL control packets and a control token. The length of each PHY control packet can be the sum of the DLL control packet length and a control token length of the control token. The PHY control packets can be encapsulated in frames. Each of the frames can include a synchronization symbol having a symbol length. The length of each frame can be the sum of the symbol length and an encapsulation length, which can be twice the length of the PHY control packet.

    Abstract translation: 提供了使用为高效传输而设计的分组化协议的串行通信。 数据链路层（DLL）控制分组可以被生成用于传输控制消息。 每个DLL控制消息分组可以具有DLL控制分组长度，并且DLL控制分组长度可以是固定长度。 可以生成物理层（PHY）控制分组。 每个PHY控制分组可以包括DLL控制分组和控制令牌中的一个。 每个PHY控制分组的长度可以是DLL控制分组长度和控制令牌的控制令牌长度之和。 PHY控制分组可以封装在帧中。 每个帧可以包括具有符号长度的同步符号。 每个帧的长度可以是符号长度和封装长度的总和，该长度可以是PHY控制数据包长度的两倍。

    PROGRAMMABLE DISTRIBUTED DATA PROCESSING IN A SERIAL LINK
    3.
    发明申请
    PROGRAMMABLE DISTRIBUTED DATA PROCESSING IN A SERIAL LINK 审中-公开
    串行链路中的可编程分布式数据处理

    公开(公告)号：WO2017136452A1

    公开(公告)日：2017-08-10

    申请号：PCT/US2017/016068

    申请日：2017-02-01

    Applicant: QUALCOMM INCORPORATED

    Inventor： KHAN, Raheel ,  CHENG, Scott ,  PHILIPPE, Pascal ,  ZETHNER, Graig ,  SEETHARAMAN, Vaidyanathan ,  BANGA, Kanwal, Preet, S. ,  BADAM, Srinivas

    IPC: H04B1/40 ,  G06F9/00 ,  H04L29/06 ,  H04L12/931

    CPC classification number: G06F13/4291 ,  G06F9/00 ,  G06F13/364 ,  H04B1/40 ,  H04L7/0008 ,  H04L7/046 ,  H04L29/06 ,  H04L67/2823 ,  H04L69/00 ,  H04L69/22

    Abstract: A serial transceiver that includes programmable distributed data processing is provided. The serial transceiver can include an ingress channel that receives serial ingress data and an egress channel that transmits serial egress data. The serial transceiver can also include first and second layers that are one and another of a transport layer, a link layer, or a physical layer (PHY). The first and second layers can include elements that process the ingress data and the egress data. The serial transceiver can also include a programmable controller, a first interconnect that connects the programmable controller to the first layer, and a second interconnect that connects the programmable controller to the second layer. The programmable controller can send first data via the first interconnect to the first layer, and the first data can be processed by one of the first layer elements.

    Abstract translation: 提供包括可编程分布式数据处理的串行收发器。 串行收发器可以包括接收串行入口数据的入口通道和发送串行出口数据的出口通道。 串行收发器还可以包括作为传输层，链路层或物理层（PHY）中的一个和另一个的第一层和第二层。 第一层和第二层可以包括处理入口数据和出口数据的元件。 串行收发器还可以包括可编程控制器，将可编程控制器连接到第一层的第一互连以及将可编程控制器连接到第二层的第二互连。 可编程控制器可以通过第一互连将第一数据发送到第一层，并且第一数据可以由第一层元件中的一个处理。

    SCALABLE, HIGH-EFFICIENCY, HIGH-SPEED SERIALIZED INTERCONNECT
    6.
    发明公开
    SCALABLE, HIGH-EFFICIENCY, HIGH-SPEED SERIALIZED INTERCONNECT 审中-公开

    公开(公告)号：EP3412016A1

    公开(公告)日：2018-12-12

    申请号：EP17705254.5

    申请日：2017-02-01

    Applicant: Qualcomm Incorporated

    Inventor： KHAN, Raheel ,  CHENG, Scott ,  PHILIPPE, Pascal ,  ROMERA, Joaquin

    IPC: H04L29/06

    Abstract: Transmission of data over a serial link based on a unidirectional clock signal is provided. A unidirectional clock signal is generated based on a first clock of a master device. The unidirectional clock signal is sent to a slave device that is connected to the serial link. The master device transmits data to the slave device over the serial link based on the first clock. The slave device receives the unidirectional clock signal from a master device. The slave device transmits data over the serial link to the master device based on the unidirectional clock signal.

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