公开(公告)号：EP3791191A2

公开(公告)日：2021-03-17

申请号：EP19720344.1

申请日：2019-04-17

Applicant: QUALCOMM INCORPORATED

Inventor： DANG, Nam ,  JAIN, Rajeev ,  NAVUBOTHU, Swarna ,  LEWIS, Alan ,  SAINT-LAURENT, Martin ,  PHAM, Tung Nang ,  TERREGROSSA, Joseph ,  GUPTA, Paras ,  MARADANI, Somasekhar

IPC: G01R19/00 ,  G01R19/32 ,  G01R19/252

公开(公告)号：WO2007067418A3

公开(公告)日：2007-06-14

申请号：PCT/US2006/045923

申请日：2006-11-30

Applicant: QUALCOMM INCORPORATED ,  DJORDJEV, Kostadin ,  HASTINGS, R., Scott ,  LEWIS, Alan ,  MIGNARD, Marc ,  CUMMINGS, William, J.

Inventor： DJORDJEV, Kostadin ,  HASTINGS, R., Scott ,  LEWIS, Alan ,  MIGNARD, Marc ,  CUMMINGS, William, J.

IPC: G09G3/34

Abstract: Charge balanced display data writing methods use write and hold cycles of opposite polarity during selected frame update periods. Spatial dithering of hold cycle signals can reduce flicker.

公开(公告)号：WO2019217040A3

公开(公告)日：2019-11-14

申请号：PCT/US2019/027777

申请日：2019-04-17

Applicant: QUALCOMM INCORPORATED

Inventor： DANG, Nam ,  JAIN, Rajeev ,  NAVUBOTHU, Swarna ,  LEWIS, Alan ,  SAINT-LAURENT, Martin ,  PHAM, Tung Nang ,  TERREGROSSA, Joseph ,  GUPTA, Paras ,  MARADANI, Somasekhar

IPC: G01R19/00 ,  G01R19/32 ,  G01R19/252

Abstract: Aspects of the disclosure are directed to voltage-based current sensing. In accordance with one aspect, voltage-based current sensing may include performing a coarse calibration of a voltage based current sensor to determine a coarse offset; performing a fine calibration of the voltage based current sensor to determine a fine offset; performing a frequency calibration of the voltage based current sensor to determine a frequency offset; and performing a transfer function calibration of the voltage based current sensor to determine a sensor transfer function using one or more of the coarse offset, the fine offset and the frequency offset; and measuring a load current using the sensor transfer function.

公开(公告)号：WO2019217040A2

公开(公告)日：2019-11-14

申请号：PCT/US2019/027777

申请日：2019-04-17

Applicant: QUALCOMM INCORPORATED

Inventor： DANG, Nam ,  JAIN, Rajeev ,  NAVUBOTHU, Swarna ,  LEWIS, Alan ,  SAINT-LAURENT, Martin ,  PHAM, Tung Nang ,  TERREGROSSA, Joseph ,  GUPTA, Paras ,  MARADANI, Somasekhar

IPC: G01R19/00 ,  G01R19/32 ,  G01R19/252

Abstract: Aspects of the disclosure are directed to voltage-based current sensing. In accordance with one aspect, voltage-based current sensing may include performing a coarse calibration of a voltage based current sensor to determine a coarse offset; performing a fine calibration of the voltage based current sensor to determine a fine offset; performing a frequency calibration of the voltage based current sensor to determine a frequency offset; and performing a transfer function calibration of the voltage based current sensor to determine a sensor transfer function using one or more of the coarse offset, the fine offset and the frequency offset; and measuring a load current using the sensor transfer function.

公开(公告)号：WO2019108360A1

公开(公告)日：2019-06-06

申请号：PCT/US2018/059726

申请日：2018-11-08

Applicant: QUALCOMM INCORPORATED

Inventor： KIDWELL JR., Donald William ,  SHENOY, Ravindra Vaman ,  LEWIS, Alan ,  FERGUSON, Christopher Feuling

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/64 ,  H01F17/00 ,  H01F41/04

Abstract: Some aspects pertain to an inductor apparatus that includes a first metal layer including a plurality of first interconnects, a second metal including a plurality of second interconnects, a first dielectric layer between the first metal layer and the second metal layer, and an inductor. The inductor includes a plurality of vias, where the plurality of vias are configured to couple the plurality of first interconnects to the plurality of second interconnects. The inductor includes a plurality of inductor loops formed by the plurality of vias, the plurality of first interconnects and the plurality of second interconnects. The inductor further includes a first magnetic layer and a second magnetic layer, located between the first interconnects and the second interconnects; and a third magnetic layer and an optional fourth magnetic layer outside of the plurality of inductor loops.

公开(公告)号：EP2033179A2

公开(公告)日：2009-03-11

申请号：EP07794970.9

申请日：2007-05-16

Applicant: Qualcomm Incorporated

Inventor： CHUI, Clarence ,  LEWIS, Alan ,  MIGNARD, Marc, M.

IPC: G09G3/34

CPC classification number: G09G3/3466 ,  G02B26/001 ,  G09G2310/0218 ,  G09G2310/0267 ,  G09G2310/06 ,  G09G2330/021

Abstract: A display array which can reduce the row connections between the display and the driver circuit and methods of manufacturing and operating the same are disclosed. In one embodiment, a display device comprises an array of MEMS display elements and a plurality of voltage dividers coupled to the array and configured to provide row output voltages to drive the array, wherein each row is connected to at least two inputs joined by a voltage divider.

公开(公告)号：EP3718153A1

公开(公告)日：2020-10-07

申请号：EP18811684.2

申请日：2018-11-08

Applicant: Qualcomm Incorporated

Inventor： KIDWELL JR., Donald William ,  SHENOY, Ravindra Vaman ,  LEWIS, Alan ,  FERGUSON, Christopher Feuling

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/64 ,  H01F17/00 ,  H01F41/04