公开(公告)号：WO2017048509A1

公开(公告)日：2017-03-23

申请号：PCT/US2016/049566

申请日：2016-08-31

Applicant: QUALCOMM INCORPORATED

Inventor： LU, Yu ,  ZHU, Xiaochun ,  LI, Xia ,  KANG, Seung, Hyuk

IPC: H01L27/22 ,  H01L43/12 ,  G11C11/16

CPC classification number: H01L27/228 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L21/823475 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Shared source line magnetic tunnel junction (MTJ) bit cells (300A) employing uniform MTJ connection patterns for reduced area are disclosed. In one aspect, a two (2) transistor, two (2) MTJ (2T2MTJ) bit cell includes a shared source line system having first and second source lines. A uniform MTJ connection pattern results in the first source line (SL1) disposed in an upper metal layer and electrically coupled to a free layer of a first MTJ (304), and the second source line (SL2) disposed in a lower metal layer and electrically coupled to a second access transistor (310). Middle segments are disposed in middle metal layers to reserve the middle metal layers for strap segments (368) of a strap cell (300B) that is used to electrically couple the first and second source lines. Electrically coupling the first and second source lines using the strap cell allows each MTJ to logically share a single source line.

Abstract translation: 公开了采用均匀MTJ连接图案以减小面积的共享源极线磁隧道结（MTJ）位单元（300A）。 一方面，两（2）晶体管，两（2）MTJ（2T2MTJ）位单元包括具有第一和第二源极线的共享源极线系统。 均匀的MTJ连接图案使得第一源极线（SL1）设置在上金属层中并电耦合到第一MTJ（304）的自由层，并且第二源极线（SL2）设置在下金属层中，并且 电耦合到第二存取晶体管（310）。 中间部分设置在中间金属层中，以保留用于电耦合第一和第二源极线的带状电池（300B）的带段（368）的中间金属层。 使用带单元电连接第一和第二源极线允许每个MTJ在逻辑上共享单个源极线。

公开(公告)号：WO2016137730A1

公开(公告)日：2016-09-01

申请号：PCT/US2016/016939

申请日：2016-02-08

Applicant: QUALCOMM INCORPORATED

Inventor： LU, Yu ,  ZHU, Xiaochun ,  KANG, Seung; Hyuk

IPC: H01L27/22 ,  H01L43/12

CPC classification number: H01L27/222 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic random access memory (MRAM) bit cells (200) employing source lines (204) and/or bit lines (206) disposed in multiple, stacked metal layers to reduce MRAM bit cell resistance are disclosed. Related methods and systems are also disclosed. In aspects disclosed herein, MRAM bit cells are provided in a memory array. The MRAM bit cells are fabricated in an integrated circuit (IC) (202) with source lines and/or bit lines formed by multiple, stacked metal layers disposed above a semiconductor layer (210) to reduce the resistance of the source lines. In this manner, if node size in the IC is scaled down, the resistance of the source lines and/or the bit lines can be maintained or reduced to avoid an increase in drive voltage that generates a write current for write operations for the MRAM bit cells.

Abstract translation: 公开了使用设置在多个堆叠金属层中的源极线（204）和/或位线（206）的磁性随机存取存储器（MRAM）位单元（200）来降低MRAM位单元电阻。 还公开了相关方法和系统。 在本文公开的方面，MRAM位单元被提供在存储器阵列中。 在集成电路（IC）（202）中制造MRAM位单元，源极线和/或位线由设置在半导体层（210）上方的多个堆叠的金属层形成，以减小源极线的电阻。 以这种方式，如果IC中的节点尺寸按比例缩小，则可以维持或减小源极线和/或位线的电阻，以避免产生用于MRAM位的写入操作的写入电流的驱动电压的增加 细胞。

公开(公告)号：WO2016089646A3

公开(公告)日：2016-06-09

申请号：PCT/US2015/062092

申请日：2015-11-23

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Xia ,  XU, Jeffrey Junhao ,  WANG, Zhongze ,  YANG, Bin ,  CHEN, Xiaonan ,  LU, Yu

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L29/78 ,  G11C16/04

Abstract: Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a silicon-doped hafnium oxide (HfO2) layer, is implemented as a ferroelectric dipole layer in a non-volatile memory device.

Abstract translation: 使用与高介电常数/金属栅极（HK / MG）工艺兼容的工艺来制造非易失性存储器件和逻辑器件以增加单元密度和更大规模集成。 诸如掺硅氧化铪（HfO 2）层的掺杂氧化物层被实现为非易失性存储器件中的铁电偶极子层。

公开(公告)号：WO2015148059A1

公开(公告)日：2015-10-01

申请号：PCT/US2015/018274

申请日：2015-03-02

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Xia ,  LEE, Kangho ,  CHEN, Wei-Chuan ,  LU, Yu ,  PARK, Chando ,  KANG, Seung Hyuk

IPC: H01L43/12

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L43/08 ,  H01L43/12

Abstract: An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode.

Abstract translation: 提供了一种改进的磁性隧道结装置和用于制造改进的磁性隧道结装置的方法。 所提供的双蚀刻工艺减少蚀刻损伤和烧蚀材料再沉积。 在一个实例中，提供了一种用于制造磁性隧道结（MTJ）的方法。 该方法包括在衬底上形成缓冲层，在衬底上形成底电极，在底电极上形成引脚层，在引脚层上形成阻挡层，并在阻挡层上形成自由层。 第一蚀刻包括蚀刻自由层，而不蚀刻阻挡层，引脚层和底部电极。 该方法还包括在自由层上形成顶部电极，以及在顶部电极上形成硬掩模层。 第二蚀刻包括蚀刻硬掩模层; 顶部电极层，阻挡层，针层和底部电极。

公开(公告)号：WO2016144436A2

公开(公告)日：2016-09-15

申请号：PCT/US2016/015932

申请日：2016-02-01

Applicant: QUALCOMM INCORPORATED

Inventor： LU, Yu ,  LI, Xia

IPC: G11C11/16 ,  G11C11/56 ,  G06F12/08

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/5607

Abstract: A device includes a first magnetic tunnel junction (MTJ) element having a first read margin and a second MTJ element having a second read margin. The first read margin is greater than twice the second read margin. The device also includes an access transistor coupled between the first MTJ element and the second MTJ element. A gate of the access transistor is coupled to a word line. The first MTJ element, the second MTJ element, and the access transistor form a multi-bit spin torque transfer magnetoresistive random access memory (STT-MRAM) memory cell.

Abstract translation: 一种装置包括具有第一读取余量的第一磁性隧道结（MTJ）元件和具有第二读取余量的第二MTJ元件。 第一个读取边距大于第二个读取边距的两倍。 该器件还包括耦合在第一MTJ元件和第二MTJ元件之间的存取晶体管。 存取晶体管的栅极耦合到字线。 第一MTJ元件，第二MTJ元件和存取晶体管形成多位自旋转矩传递磁阻随机存取存储器（STT-MRAM）存储单元。

公开(公告)号：WO2016137669A1

公开(公告)日：2016-09-01

申请号：PCT/US2016/015790

申请日：2016-01-29

Applicant: QUALCOMM INCORPORATED

Inventor： LU, Yu ,  BAO, Junjing ,  LI, Xia ,  KANG, Seung Hyuk

IPC: H01L43/08 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/16 ,  H01L23/544 ,  H01L43/08 ,  H01L43/12 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A semiconductor device includes a resistive memory device bottom electrode (118, 120) formed on an interconnect (104, 108). The bottom electrode comprised of cobalt tungsten phosphorus (CoWP), preferably formed by electroless deposition, is particularly suited for magnetic tunnel junction MRAM devices (126, 128).

Abstract translation: 半导体器件包括形成在互连（104,108）上的电阻性存储器件底部电极（118,120）。 由钴钨磷（CoWP）组成的底部电极优选通过无电沉积形成，特别适用于磁性隧道结MRAM器件（126,128）。

公开(公告)号：WO2017222723A1

公开(公告)日：2017-12-28

申请号：PCT/US2017/034133

申请日：2017-05-24

Applicant: QUALCOMM INCORPORATED

Inventor： LU, Yu ,  CHEN, Wei-Chuan ,  KAN, Jimmy, Jianan ,  KANG, Seung, Hyuk

IPC: H01L43/08 ,  H01L43/12 ,  G11C11/16

CPC classification number: H01L27/228 ,  G11C11/16 ,  H01L21/0273 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76879 ,  H01L43/12

Abstract: High aspect ratio vertical interconnect access (via) interconnections in magnetic random access memory (MRAM) bit cells are disclosed.In one aspect, an exemplary MRAM bit cell includes a coupling column interconnecting an access transistor and a magnetic tunnel junction (MTJ) therein. The coupling column is disposed across a plurality of interconnection layers.In one aspect, the coupling column comprises a high aspect ratio via.In another aspect, the high aspect ratio via is connected directly between a drain contact coupled to a drain of the access transistor and to an end electrode of the MTJ such that no interconnection line and/or interconnection island is provided in the coupling column.In certain aspects, the coupling column may be disposed between an interconnection line and an adjacent interconnection line without increasing an existing interconnection line pitch, thus allowing for a reduction in MRAM bit cell pitch.

Abstract translation: 公开了磁性随机存取存储器（MRAM）位单元中的高纵横比垂直互连访问（通孔）互连。一方面，示例性MRAM位单元包括互连访问晶体管和 磁性隧道结（MTJ）。 耦合列横跨多个互连层设置。在一个方面中，耦合列包括高纵横比通孔。在另一方面，高纵横比通孔直接连接到耦合到存取晶体管的漏极的漏极触点 并且连接到MTJ的端电极，使得在耦合列中不设置互连线和/或互连岛。在某些方面，耦合列可以设置在互连线和相邻互连线之间，而不增加现有的互连线 这样可以减少MRAM位元间距。

公开(公告)号：WO2017027148A1

公开(公告)日：2017-02-16

申请号：PCT/US2016/041790

申请日：2016-07-11

Applicant: QUALCOMM INCORPORATED

Inventor： LU, Yu ,  KANG, Seung Hyuk

IPC: H01L43/12 ,  H01L27/22

CPC classification number: H01L27/222 ,  G06F17/5045 ,  H01L23/5226 ,  H01L23/528 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A method of fabrication of a device (100) includes forming a first metallization layer (102) that is coupled to a logic device of the device. The method further includes forming a second metallization layer (161) that is coupled to a magnetoresistive random access memory (MRAM) module (160) of the device. The second metallization layer is independent of the first metallization layer.

Abstract translation: 一种制造器件（100）的方法包括形成耦合到器件的逻辑器件的第一金属化层（102）。 该方法还包括形成耦合到该器件的磁阻随机存取存储器（MRAM）模块（160）的第二金属化层（161）。 第二金属化层独立于第一金属化层。

公开(公告)号：WO2016200510A1

公开(公告)日：2016-12-15

申请号：PCT/US2016/030705

申请日：2016-05-04

Applicant: QUALCOMM INCORPORATED

Inventor： LU, Yu ,  CHEN, Wei-Chuan ,  KANG, Seung Hyuk

IPC: H01L43/08 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: The proposed semiconductor device (600) includes a magnetoresistive random-access memory (MRAM) trench (632) having a first conductive barrier liner (650) and an underlying second conductive barrier liner (660), the MRAM trench landing on a hard mask (644) of a magnetic tunnel junction (MTJ) within an MTJ region (630). The semiconductor device also includes a logic trench (622) on a logic via (624), both also having the first conductive barrier liner (650). The logic via lands on a portion (626) of a conductive interconnect (Mx) within a logic region (620). The device is made by fabricating the MRAM trench independently from fabricating the logic trench and logic via, followed by simultaneously filling said trenches and via.

Abstract translation: 所提出的半导体器件（600）包括具有第一导电阻挡衬垫（650）和下面的第二导电阻挡衬垫（660）的磁阻随机存取存储器（MRAM）沟槽（632），所述MRAM沟槽在硬掩模 644）在MTJ区域（630）内的磁性隧道结（MTJ）。 半导体器件还包括逻辑通孔（624）上的逻辑沟槽（622），两者也具有第一导电阻挡衬垫（650）。 在逻辑区域（620）内的导电互连（Mx）的部分（626）上的逻辑电路。 该器件通过制造MRAM沟槽而制造，独立于制造逻辑沟槽和逻辑通孔，随后同时填充所述沟槽和通孔。

公开(公告)号：WO2016175956A1

公开(公告)日：2016-11-03

申请号：PCT/US2016/024448

申请日：2016-03-28

Applicant: QUALCOMM INCORPORATED

Inventor： ZHU, Xiaochun ,  LU, Yu ,  PARK, Chando ,  KANG, Seung, Hyuk

IPC: H01L27/22 ,  G11C11/02

CPC classification number: G11C11/1659 ,  G11C11/02 ,  G11C11/161 ,  H01L27/228

Abstract: Magnetic tunnel junction (MTJ) memory bit cells that decouple source line layout from access transistor node size to facilitate reduced contact resistance are disclosed. In one example, an MTJ memory bit cell (500B) is provided that includes a source plate (508) disposed above and in contact with a source contact (502) for a source node (S) of an access transistor (510). A source line (516) is disposed above and in electrical contact with the source plate to electrically connect the source line to the source node. The source plate allows the source line to be provided in a higher metal level from the source and drain contacts of the access transistor such that the source line is not in physical contact with (i.e., decoupled from) the source contact. This allows pitch between the source line and drain column to be relaxed from the width of the source and drain nodes without having to increase contact resistance.

Abstract translation: 公开了将源极线布局与存取晶体管节点尺寸分离以便于降低接触电阻的磁隧道结（MTJ）存储器位单元。 在一个示例中，提供MTJ存储器位单元（500B），其包括设置在存取晶体管（510）的源极（S）的源极触点（502）上方并与之接触的源极板（508）。 源极线（516）设置在源极板之上并与源极电接触以将源极线电连接到源极节点。 源极板允许源极线从存取晶体管的源极和漏极触点提供在更高的金属电平，使得源极线不与源极接触物理接触（即，去耦合）。 这允许源极线和漏极列之间的间距从源极和漏极节点的宽度松弛，而不必增加接触电阻。