中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

76 records (took 0.029 seconds)

    PACKAGE COMPRISING CHANNEL INTERCONNECTS LOCATED BETWEEN SOLDER INTERCONNECTS
    1.
    发明申请
    PACKAGE COMPRISING CHANNEL INTERCONNECTS LOCATED BETWEEN SOLDER INTERCONNECTS 审中-公开

    公开(公告)号：WO2023091285A1

    公开(公告)日：2023-05-25

    申请号：PCT/US2022/048192

    申请日：2022-10-28

    Applicant: QUALCOMM INCORPORATED

    Inventor： PATIL, Aniket ,  LISK, Durodami ,  WE, Hong Bok ,  PAYNTER, Charles David

    IPC: H01L23/538 ,  H01L25/10 ,  H05K1/14 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

    Abstract: A device comprising a first package and a second package coupled to the first package through a first plurality of solder interconnects. The first package includes a first substrate comprising at least one first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes a second substrate comprising at least one second dielectric layer and a second plurality of interconnects, a second integrated device coupled to a first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate through a second plurality of solder interconnects and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects is located between solder interconnects from the second plurality of solder interconnects.

    PACKAGE WITH A SUBSTRATE COMPRISING PERIPHERY INTERCONNECTS
    2.
    发明申请
    PACKAGE WITH A SUBSTRATE COMPRISING PERIPHERY INTERCONNECTS 审中-公开

    公开(公告)号：WO2022164559A1

    公开(公告)日：2022-08-04

    申请号：PCT/US2021/064902

    申请日：2021-12-22

    Applicant: QUALCOMM INCORPORATED

    Inventor： PATIL, Aniket ,  WE, Hong Bok

    IPC: H01L23/538 ,  H01L21/48 ,  G11C5/06

    Abstract: A package comprising a substrate, a first integrated device and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects, a solder resist layer, and a plurality of periphery interconnects located over the solder resist layer. The first integrated device is coupled to the substrate. The second integrated device is coupled to the substrate. The second integrated device is configured to be electrically coupled to the first integrated device through the plurality of periphery interconnects.

    SUBSTRATE WITH ACTIVE AND/OR PASSIVE DEVICES ATTACHED THERETO
    3.
    发明申请
    SUBSTRATE WITH ACTIVE AND/OR PASSIVE DEVICES ATTACHED THERETO 审中-公开

    公开(公告)号：WO2022072101A1

    公开(公告)日：2022-04-07

    申请号：PCT/US2021/048248

    申请日：2021-08-30

    Applicant: QUALCOMM INCORPORATED

    Inventor： PATIL, Aniket ,  WE, Hong Bok ,  BUOT, Joan Rey Villarba

    IPC: H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H01L23/538

    Abstract: Terminal connection routing on top of a substrate surface connects to component terminals to and from PMIC devices and provides a novel structure to connect surface mount technology (SMT) passive device terminals on an SMT layer (such as a Cu bar mesh) that uses the 3D space available near to components to lower resistance / lower inductive path and provides a shorter path, SIP form factor reduction, a component placement density increase, creates an additional PDN layer for connectivity and, if the routing is encapsulated in a mold, protects the metal in the connection from oxidation.

    SEMICONDUCTOR PACKAGE COMPRISING A SUBSTRATE AND A HIGH-DENSITY INTERCONNECT STRUCTURE COUPLED THERETO
    5.
    发明申请
    SEMICONDUCTOR PACKAGE COMPRISING A SUBSTRATE AND A HIGH-DENSITY INTERCONNECT STRUCTURE COUPLED THERETO 审中-公开

    公开(公告)号：WO2021173825A1

    公开(公告)日：2021-09-02

    申请号：PCT/US2021/019654

    申请日：2021-02-25

    Applicant: QUALCOMM INCORPORATED

    Inventor： PATIL, Aniket ,  WANG, Zhijie ,  WE, Hong, Bok

    IPC: H01L25/065 ,  H01L21/683 ,  H01L23/00

    Abstract: A package comprising a substrate, an integrated device, and an interconnect structure. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects for providing at least one electrical connection to a board. The integrated device is coupled to the first surface of the substrate. The interconnect structure is coupled to the first surface of the substrate. The integrated device, the interconnect structure and the substrate are coupled together in such a way that when a first electrical signal travels between the integrated device and the board, the first electrical signal travels through at least the substrate, then through the interconnect structure and back through the substrate.

    CIRCULAR BOND FINGER PAD
    10.
    发明申请
    CIRCULAR BOND FINGER PAD 审中-公开

    公开(公告)号：WO2022164565A1

    公开(公告)日：2022-08-04

    申请号：PCT/US2021/065329

    申请日：2021-12-28

    Applicant: QUALCOMM INCORPORATED

    Inventor： BUOT, Joan Rey Villarba ,  PATIL, Aniket ,  WANG, Zhijie ,  WE, Hong Bok

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

    Abstract: Disclosed are examples of integrated circuit (IC) packages. Each IC package may include a flip-chip (FC) die on a substrate, a wire bond die above the FC die, a wire bond connected to the wire bond die, and a mold on the substrate and encapsulating the FC die, the wire bond die, and the wire bond. The substrate may include at least a first metallization layer comprising a first substrate layer, a trace on the first substrate layer and routed within the first metallization layer to electrically couple with one or more FC interconnects of the FC die, and a bond finger pad formed on the trace. The bond finger pad may be circular. The wire bond may electrically connect to the trace such that the wire bond die is electrically coupled with the FC die through the wire bond, the bond finger pad, and the trace.

Patent Agency Ranking