公开(公告)号：WO2021178078A1

公开(公告)日：2021-09-10

申请号：PCT/US2021/015493

申请日：2021-01-28

Applicant: QUALCOMM INCORPORATED

Inventor： WE, Hong Bok ,  PATIL, Aniket ,  HSU, Marcus ,  RAE, David Fraser

IPC: H01L21/60 ,  H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L25/16 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/214 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3511

Abstract: Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die ("IC die") module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package (200) are stacked and bonded together in a back-to-back, top (204(2), 204(3)) and bottom (204(1)) IC die configuration in an IC die module, which can minimize the overall height of the IC package. The metallization structure is split between separate top (206T) and bottom (206B) metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects (210,212) on respective inner and outer surfaces for respective die and external electrical interconnections. In other exemplary aspects, the top and bottom metallization structures can include redistribution layers (RDLs) to provide increased electrical conductivity between die interconnects and substrate interconnects.

公开(公告)号：WO2016191195A1

公开(公告)日：2016-12-01

申请号：PCT/US2016/033264

申请日：2016-05-19

Applicant: QUALCOMM INCORPORATED

Inventor： RAE, David Fraser ,  KESER, Lizabeth Ann ,  ALVARADO, Reynante Tamunan

IPC: H01L25/16 ,  H01L21/60 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L25/16 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/75 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2224/83

Abstract: An integrated package may be manufactured in a die (110) face up orientation with a component (140) proximate to the attached die by creating a cavity (130) in the mold compound (120) during fabrication. The cavity is created with an adhesive layer (132) on the bottom to hold a component such that the top surface of the component is co-planar with the top surface of the attached die. This may allow backside grinding to take place that will not damage the component because the top surface alignment between the attached die and the component prevents the depth of the cavity from extending into the portion of the package that is ground away.

Abstract translation: 可以通过在制造期间在模制化合物（120）中产生空腔（130）而将模具（110）面向上取向制造成与组件（140）靠近所附接的模具。 在底部产生具有粘合剂层（132）的空腔，以保持部件，使得部件的顶部表面与附接的模具的顶表面共面。 这可能允许进行不会损坏部件的背面研磨，因为附接的模具和部件之间的顶部表面对准防止空腔的深度延伸到被剥离的包装的部分中。

公开(公告)号：WO2022010593A1

公开(公告)日：2022-01-13

申请号：PCT/US2021/034914

申请日：2021-05-28

Applicant: QUALCOMM INCORPORATED

Inventor： HAN, Jeahyeong ,  RAE, David Fraser ,  KUMAR, Rajneesh

IPC: H01L23/552 ,  H01L25/16

Abstract: Packages are configured to include an electromagnetic interference (EMI) shield. According to one example, a package includes a substrate (302), an electrical component (304), and an EMI shield (602). The substrate includes a first surface and a second surface. The electrical component may be coupled to the first side of the substrate. The EMI shield is formed with at least one passive device (312). The at least one passive device is coupled to the first surface of the substrate. The at least one passive device is located laterally to the at least one electrical component, and extends along at least a portion of the electrical component. Other aspects, embodiments, and features are also included.

公开(公告)号：WO2021066983A1

公开(公告)日：2021-04-08

申请号：PCT/US2020/048872

申请日：2020-09-01

Applicant: QUALCOMM INCORPORATED

Inventor： PATIL, Aniket ,  WE, Hong Bok ,  RAE, David Fraser

IPC: H01L23/498 ,  H01L23/538 ,  H05K3/46

Abstract: Examples of semiconductor packages with stacked RDLs described herein may include, for example, a first RDL comprising multiple RDL layers coupled to a second RDL comprising multiple RDL layers using copper pillars and an underfill in place of a conventional substrate. The examples herein may use RDLs instead of substrates to achieve smaller design feature size (x, y dimensions reduction), thinner copper layers and less metal usage (z dimension reduction), flexibility to attach semiconductor dies and surface mount devices (SMD) on either side of the package, and less number of built-up RDL layers.

公开(公告)号：WO2016205563A1

公开(公告)日：2016-12-22

申请号：PCT/US2016/037931

申请日：2016-06-16

Applicant: QUALCOMM INCORPORATED

Inventor： KESER, Lizabeth Ann ,  RAE, David Fraser ,  GUPTA, Piyush

IPC: H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/31116 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76802 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/89 ,  H01L24/96 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/08245 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/48471 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/8538 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06579 ,  H01L2924/00014 ,  H01L2924/12 ,  H01L2924/1304 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/32245 ,  H01L2224/48247

Abstract: An integrated circuit (IC) package that includes a first die, a wire bond coupled to the first die, a first encapsulation layer that at least partially encapsulates the first die and the wire bond, a second die, a redistribution portion coupled to the second die, and a second encapsulation layer that at least partially encapsulates the second die. In some implementations, the wire bond is coupled to the redistribution portion. In some implementations, the integrated circuit (IC) package further includes a package interconnect that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package further includes a via that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package has a height of about 500 microns (μm) or less.

Abstract translation: 一种集成电路（IC）封装，其包括第一管芯，耦合到所述第一管芯的引线接合，至少部分地封装所述第一管芯和所述引线接合的第一封装层，第二管芯，耦合到所述第二管芯的再分配部分 并且至少部分地封装第二管芯的第二封装层。 在一些实施方式中，引线接合耦合到再分配部分。 在一些实现中，集成电路（IC）封装进一步包括由第二封装层至少部分封装的封装互连。 在一些实现中，集成电路（IC）封装还包括至少部分地由第二封装层封装的通孔。 在一些实现中，集成电路（IC）封装具有约500微米（μm）或更小的高度。

公开(公告)号：EP3298625A1

公开(公告)日：2018-03-28

申请号：EP16728156.7

申请日：2016-05-19

Applicant: Qualcomm Incorporated

Inventor： RAE, David Fraser ,  KESER, Lizabeth Ann ,  ALVARADO, Reynante Tamunan

IPC: H01L21/60 ,  H01L25/16 ,  H01L23/538 ,  H01L25/10 ,  H01L21/56

CPC classification number: H01L21/768 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/81

Abstract: A package may include a die proximate to a structure having a substrate with interconnects and a first component coupled to the interconnects. The die may be face up or face down. The package may include a first redistribution layer coupling the die to the interconnects of the structure and a mold compound covering the die and maybe the structure.

公开(公告)号：EP2973700A1

公开(公告)日：2016-01-20

申请号：EP14718819.7

申请日：2014-03-11

Applicant: Qualcomm Incorporated

Inventor： KIM, Chin-Kwan ,  BCHIR, Omar James ,  SHAH, Milind Pravin ,  HSU, Marcus Bernard ,  RAE, David Fraser

IPC: H01L25/10 ,  H01L23/13 ,  H01L21/56 ,  H01L25/03

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: To achieve a package-on-package having an advantageously reduced height, a first package substrate (200,700) has a window sized (215,715) to receive a second package die (305,715). The first package substrate (200,700) interconnects to the second package substrate (110) through a plurality of package-to-package interconnects (400) such that the first and second substrates are separated by a gap. The second package die has a thickness greater than the gap such that the second package die is at least partially disposed within the first package substrate's window.

公开(公告)号：WO2021162816A1

公开(公告)日：2021-08-19

申请号：PCT/US2021/013176

申请日：2021-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： RAE, David Fraser ,  HOLMES, John ,  HSU, Marcus ,  KANG, Kuiwon ,  SODHI, Avantika

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L23/433

Abstract: A package that includes a first substrate, an integrated device coupled to the first substrate, a second substrate coupled to the integrated device, and an encapsulation layer located between the first substrate and the second substrate. The second substrate is configured to operate as a heat spreader. The second substrate is configured to be free of an electrical connection with the integrated device.

公开(公告)号：WO2016191193A1

公开(公告)日：2016-12-01

申请号：PCT/US2016/033261

申请日：2016-05-19

Applicant: QUALCOMM INCORPORATED

Inventor： RAE, David Fraser ,  KESER, Lizabeth Ann ,  ALVARADO, Reynante Tamunan

IPC: H01L21/60 ,  H01L25/16 ,  H01L23/538 ,  H01L25/10 ,  H01L21/56

CPC classification number: H01L21/768 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/81

Abstract: A package including a die (110) proximate to a structure (130) having a substrate (131) with interconnects (132) and a first component (133) coupled to the interconnects. The substrate is oriented at an angle greater than 10 degrees relative to a face of the die. The die (110) may be face up or face down. The package includes a first redistribution layer (150) coupling the die to the interconnects (132) of the structure and a mold compound (120) at least partially covering the die (110) and the structure (130).

Abstract translation: 一种包括靠近结构（130）的管芯（110），其具有带有互连件（132）的衬底（131）和耦合到所述互连件的第一部件（133）。 基板相对于模具的表面以大于10度的角度定向。 模具（110）可以面向上或朝下。 包装包括将管芯连接到结构的互连件（132）的第一再分配层（150）和至少部分地覆盖管芯（110）和结构（130）的模具化合物（120）。

公开(公告)号：WO2016018950A1

公开(公告)日：2016-02-04

申请号：PCT/US2015/042542

申请日：2015-07-28

Applicant: QUALCOMM INCORPORATED

Inventor： KUMAR, Rajneesh ,  JOMAA, Houssam Wafic ,  RAE, David Fraser ,  ROUHANA, Layal ,  BCHIR, Omar James

IPC: H01L23/498

CPC classification number: H01L21/76852 ,  H01L21/4825 ,  H01L21/76879 ,  H01L23/4952 ,  H01L23/49527 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/53204 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/00014

Abstract: Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.

Abstract translation: 一些特征涉及集成器件，其包括第一衬底，耦合到第一衬底的第一阻焊层，耦合到第一阻焊层的第二阻焊层，以及第一和第二阻焊层中的开口， 开口，其包括完全被第二阻焊层覆盖的侧壁，其中第二阻焊层的侧壁覆盖第一阻焊层的侧壁。 在一些实施方案中，开口至少部分地填充有导电材料。 导电材料包括焊料和/或互连中的一种。 集成器件包括耦合到导电材料的第一互连。 第一互连是至少焊料和/或互连球之一。 在一些实施方案中，集成器件包括耦合到衬底的焊盘和耦合到焊盘的第一互连。