公开(公告)号：WO2015200604A1

公开(公告)日：2015-12-30

申请号：PCT/US2015/037645

申请日：2015-06-25

Applicant: QUALCOMM INCORPORATED

Inventor： GERBER, Nir ,  REMPLE, Terrence, Brian ,  DEANS, Russell, Coleman ,  BEN SHOSHAN, Moshe ,  MURPHY, Glenn, Aaron

IPC: G06F13/38 ,  G06F1/32

CPC classification number: G06F1/324 ,  G06F1/325 ,  G06F1/3253 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D50/20

Abstract: Systems and methods for conserving power in a universal serial bus (USB) are disclosed. In one aspect, when a USB device enters a low power mode (e.g., U1 or U2), a clock associated with the USB device is modified to also enter a low power mode. Since the PIPE interface associated with the USB device still requires a clock signal, the low power clock mode must still be able to provide the PIPE interface with a clock signal. However, the clock signal to the PIPE interface does not need to be the same frequency or accuracy as the clock signal used by the USB interface. The modification to the clock changes the clock frequency to a low frequency compared to the normal clock frequency. By using a low frequency clock for the PIPE interface, power is conserved while preserving the functionality of the PIPE interface.

Abstract translation: 公开了在通用串行总线（USB）中节省功率的系统和方法。 一方面，当USB设备进入低功率模式（例如，U1或U2）时，与USB设备关联的时钟被修改为也进入低功率模式。 由于与USB设备相关联的PIPE接口仍然需要时钟信号，所以低功耗时钟模式仍然能够为PIPE接口提供时钟信号。 然而，到PIPE接口的时钟信号不需要与USB接口使用的时钟信号相同的频率或精度。 与正常时钟频率相比，时钟的修改将时钟频率更改为低频。 通过为PIPE接口使用低频时钟，节省功率，同时保持PIPE接口的功能。

公开(公告)号：WO2017095593A1

公开(公告)日：2017-06-08

申请号：PCT/US2016/060543

申请日：2016-11-04

Applicant: QUALCOMM INCORPORATED

Inventor： GERBER, Nir ,  BERMAN, Itamar ,  CASSUTO, Yair, Shmuel ,  REMPLE, Terrence, Brian

IPC: G06F13/38

CPC classification number: G06F13/4282 ,  G06F13/382 ,  G06F13/385

Abstract: Techniques for increased data flow in Universal Serial Bus (USB) cables are disclosed. In one aspect, two super-speed lanes may be enabled on a single USB cable. In an exemplary, non-limiting aspect, the USB cable is a Type-C cable. In further non-limiting aspects, the super-speed lanes may be present even if there is no USB 2.0 lane present on the D+/D- pins of the USB cable. Use of the second super-speed lane increases data throughput. Eliminating the requirement that the D+/D- pins be used for USB 2.0 data allows greater flexibility in the use of the USB connection because audio or video data may be sent over the D+/D- pins instead of USB 2.0 data. Further, the use of the two super-speed lanes allows a single computing element to operate as a host on one lane and a device on a second lane.

Abstract translation: 公开了用于增加通用串行总线（USB）电缆中的数据流的技术。 在一个方面，可以在单个USB电缆上启用两个超高速通道。 在示例性的非限制性方面中，USB电缆是C型电缆。 在进一步的非限制性方面，即使在USB电缆的D + / D-引脚上不存在USB 2.0通道，超高速通道也可以存在。 使用第二条超高速车道可提高数据吞吐量。 由于音频或视频数据可能通过D + / D-引脚而不是USB 2.0数据传输，因此消除了将D + / D-引脚用于USB 2.0数据的要求，因此可以更灵活地使用USB连接。 此外，两个超高速通道的使用允许单个计算元件作为一个通道上的主机和另一个通道上的设备来操作。

公开(公告)号：WO2016007713A1

公开(公告)日：2016-01-14

申请号：PCT/US2015/039691

申请日：2015-07-09

Applicant: QUALCOMM INCORPORATED

Inventor： KULKARNI, Ameya ,  PATNAIK, Devdutt ,  REMPLE, Terrence, Brian ,  CHOI, Jay, Yu Jae ,  HAMIDI, Madjid, Abdul

IPC: G06F13/38

CPC classification number: G01R17/02 ,  G01R19/0092 ,  G06F13/387 ,  H02J7/0052 ,  H02J7/007 ,  H02J2007/0062

Abstract: Apparatuses and methods to distinguish proprietary, non-floating and floating chargers for regulating charging current are disclosed. In one aspect, a charger detection circuit is provided in a portable electronic device. The charger detection circuit is configured to detect whether a connected Universal Serial Bus (USB) charger is compliant with a USB battery charging specification. If the connected USB charger is non-compliant with the USB battery charging specification, the charger detection circuit is configured to further detect if the non-complaint USB charger is a non-compliant floating USB charger or a non-compliant proprietary USB charger. If the connected USB charger is determined to be a non-compliant proprietary USB charger, the portable electronic device can be configured to draw up to a maximum charging current according to the USB battery charging specification.

Abstract translation: 公开了用于区分用于调节充电电流的专有，非浮动和浮动充电器的装置和方法。 一方面，在便携式电子设备中提供充电器检测电路。 充电器检测电路被配置为检测连接的通用串行总线（USB）充电器是否符合USB电池充电规范。 如果所连接的USB充电器不符合USB电池充电规格，则充电器检测电路配置为进一步检测不投诉的USB充电器是不兼容的浮动USB充电器还是非兼容专有USB充电器。 如果连接的USB充电器被确定为不符合规定的专有USB充电器，便携式电子设备可以配置为根据USB电池充电规格绘制最大充电电流。

公开(公告)号：WO2016182802A1

公开(公告)日：2016-11-17

申请号：PCT/US2016/030643

申请日：2016-05-04

Applicant: QUALCOMM INCORPORATED

Inventor： AMARILIO, Lior ,  REMPLE, Terrence, Brian

IPC: G06F13/40

CPC classification number: H04R1/1033 ,  G06F3/162 ,  G06F13/4045 ,  H04B1/3833 ,  H04R3/005 ,  H04R3/12

Abstract: Low latency transmission systems and methods for long distances in SOUNDWIRE systems are disclosed. In an exemplary aspect, a SOUNDWIRE sub-system is coupled to a long cable through a bridge. The bridge converts SOUNDWIRE signals to signals for transmission over the long cable and converts the signals from the long cable to the SOUNDWIRE signals for transmission in the SOUNDWIRE sub-system. Conversion between signal types may include concatenating signals of a similar type into a group that is serially transmitted over the long cable. Concatenation of bit slots in this manner consumes minimal overhead in bus turnaround, thereby reducing latency. In further aspects, the functionality of the bridge may be incorporated into a headset or a mobile terminal.

Abstract translation: 公开了在SOUNDWIRE系统中用于长距离的低延迟传输系统和方法。 在示例性方面，SOUNDWIRE子系统通过桥耦合到长电缆。 桥将SOUNDWIRE信号转换成信号以通过长电缆传输，并将信号从长电缆转换为SOUNDWIRE信号，以在SOUNDWIRE子系统中传输。 信号类型之间的转换可以包括将类似类型的信号连接成通过长电缆串行传输的组。 以这种方式连接位插槽在总线周转中消耗最少的开销，从而减少延迟。 在另外的方面，桥接器的功能可以被并入耳机或移动终端。

公开(公告)号：WO2016069206A1

公开(公告)日：2016-05-06

申请号：PCT/US2015/053938

申请日：2015-10-05

Applicant: QUALCOMM INCORPORATED

Inventor： REMPLE, Terrence, Brian ,  ELLIS, Duane, Eugene ,  SHAHROKHINIA, Sassan ,  WONG, Victor, Kam Kin

IPC: G06F11/267

CPC classification number: G06F11/221 ,  G06F11/263 ,  G06F11/267

Abstract: Embedded Universal Serial Bus (USB) debug (EUD) for multi-interfaced debugging in electronic systems are disclosed. Electronic systems contain complex integrated circuits (ICs) that require extensive testing and debugging to ensure good quality and performance. In exemplary aspects, an EUD is provided in an electronic system. The EUD is configured to send control information to and/or collect debugging information from multiple internal debugging interfaces in the electronic system. The EUD is also configured to convert the debugging information into a USB format so that the debugging information can be externally accessed through a USB interface provided by the electronic system. The EUD can provide non-invasive monitoring of the electronic system. The electronic system is able to use a USB port for communications in a mission mode while EUD is enabled. Additionally, the electronic system can turn on or off all system clocks during power-saving mode while the EUD continues to function.

Abstract translation: 公开了用于电子系统中多接口调试的嵌入式通用串行总线（USB）调试（EUD）。 电子系统包含复杂的集成电路（IC），需要大量测试和调试，以确保良好的质量和性能。 在示例性方面，在电子系统中提供EUD。 EUD配置为从电子系统的多个内部调试接口发送控制信息和/或收集调试信息。 EUD还配置为将调试信息转换为USB格式，以便可以通过电子系统提供的USB接口从外部访问调试信息。 EUD可以为电子系统提供非侵入性监测。 当启用EUD时，电子系统能够使用USB端口进行任务模式的通信。 另外，在EUD继续工作的同时，电源系统可以在省电模式下打开或关闭所有系统时钟。

公开(公告)号：EP3167376B1

公开(公告)日：2020-01-01

申请号：EP15739744.9

申请日：2015-07-09

Applicant: Qualcomm Incorporated

Inventor： KULKARNI, Ameya ,  PATNAIK, Devdutt ,  REMPLE, Terrence, Brian ,  CHOI, Jay, Yu Jae ,  HAMIDI, Madjid, Abdul

IPC: G06F13/38

公开(公告)号：EP3158461A1

公开(公告)日：2017-04-26

申请号：EP15733958.1

申请日：2015-06-16

Applicant: Qualcomm Incorporated

Inventor： REMPLE, Terrence, Brian ,  DANG, Nam, Van ,  SHAHROKHINIA, Sassan

IPC: G06F13/42

CPC classification number: G06F13/426 ,  G06F13/382 ,  G06F13/385 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0038 ,  G06F2213/3812

Abstract: A link layer to physical layer (PHY) serial interface is disclosed. In one aspect, a system on a chip (SoC) integrated circuit (IC) includes a link layer circuit, and a remote IC includes a Universal Serial Bus (USB) PHY circuit. A bus having four or fewer wires connects the two ICs. A link bridge communicates with the link layer circuit and serializes USB Transceiver Macrocell Interface (UTMI) signaling received from the link layer circuit as high speed (HS) USB messages for transmission to the remote IC. The link bridge also receives HS messages from the USB PHY circuit on the remote IC. The link bridge deserializes the HS messages to extract UTMI signaling and passes the extracted UTMI signaling to the link layer circuit.

Abstract translation: 公开了链路层到物理层（PHY）串行接口。 在一个方面，片上系统（SoC）集成电路（IC）包括链路层电路，并且远程IC包括通用串行总线（USB）PHY电路。 具有四根或更少线的总线连接两个IC。 链路桥与链路层电路进行通信，并将从链路层电路接收到的USB收发器宏蜂窝接口（UTMI）信令作为高速（HS）USB消息串行化，以发送到远程IC。 链路桥还接收来自远程IC上的USB PHY电路的HS消息。 链路桥将HS消息解串行化以提取UTMI信令并将提取的UTMI信令传递给链路层电路。

公开(公告)号：EP3167376A1

公开(公告)日：2017-05-17

申请号：EP15739744.9

申请日：2015-07-09

Applicant: Qualcomm Incorporated

Inventor： KULKARNI, Ameya ,  PATNAIK, Devdutt ,  REMPLE, Terrence, Brian ,  CHOI, Jay, Yu Jae ,  HAMIDI, Madjid, Abdul

IPC: G06F13/38

Abstract: Apparatuses and methods to distinguish proprietary, non-floating and floating chargers for regulating charging current are disclosed. In one aspect, a charger detection circuit is provided in a portable electronic device. The charger detection circuit is configured to detect whether a connected Universal Serial Bus (USB) charger is compliant with a USB battery charging specification. If the connected USB charger is non-compliant with the USB battery charging specification, the charger detection circuit is configured to further detect if the non-complaint USB charger is a non-compliant floating USB charger or a non-compliant proprietary USB charger. If the connected USB charger is determined to be a non-compliant proprietary USB charger, the portable electronic device can be configured to draw up to a maximum charging current according to the USB battery charging specification.

Abstract translation: 装置和方法来区分专有的，非浮动及浮动充电器，用于调节的充电电流被游离缺失光盘。 在一个方面中，充电器检测电路中的便携式电子设备提供的。 充电器检测电路被配置为检测是否连接的通用串行总线（USB）充电器符合一个USB电池充电规范。 如果所连接的USB充电器为非符合USB电池充电说明书中，充电器检测电路被配置つweiterer检测如果非投诉USB充电器是一个非依从浮动USB充电器或不符合规定的专有USB充电器。 如果连接的USB充电器确定性开采是一个非顺从专有USB充电器，便携式电子设备可以被配置成制定到一个最大充电电流gemäß到USB电池充电规范。

公开(公告)号：WO2016018753A1

公开(公告)日：2016-02-04

申请号：PCT/US2015/042006

申请日：2015-07-24

Applicant: QUALCOMM INCORPORATED

Inventor： PATNAIK, Devdutt ,  CHOI, Jay, Yu Jae ,  REMPLE, Terrence, Brian

IPC: G06F1/26

CPC classification number: H02J7/007 ,  G06F1/266 ,  G06F11/2289 ,  G06F11/3027 ,  G06F11/3051 ,  G06F11/3062 ,  G06F13/4282 ,  G06F2213/0042 ,  H02J7/0004 ,  H02J7/0052 ,  H02J2007/0062

Abstract: Apparatuses, methods, and systems for enabling higher current charging of Universal Serial Bus (USB) Specification Revision 2.0 (USB 2.0) portable electronic devices from USB 3.x hosts are disclosed. In one aspect, a USB 2.0 controller is provided in a USB 2.0 portable device. A USB 3.x controller is provided in a USB 3.x host. The USB 2.0 controller is configured to draw a higher charging current than specified in USB 2.0 for the USB 2.0 portable device over a USB 2.0 cable. In order to draw the higher charging current without violating USB 2.0, the USB 2.0 controller is configured to use one or more reserved elements in an existing USB 2.0 descriptor(s) or bitmap(s) to indicate a higher charging current request from the USB 2.0 controller.

Abstract translation: 公开了用于实现USB 3.x主机的通用串行总线（USB）规范2.0版（USB 2.0）便携式电子设备的更高电流充电的装置，方法和系统。 一方面，在USB 2.0便携式设备中提供USB 2.0控制器。 USB 3.x主机中提供USB 3.x控制器。 USB 2.0控制器配置为通过USB 2.0电缆为USB 2.0便携式设备绘制比USB 2.0中规定的更高的充电电流。 为了在不违反USB 2.0的情况下绘制更高的充电电流，USB 2.0控制器被配置为使用现有USB 2.0描述符或位图中的一个或多个保留元件来指示来自USB的更高的充电电流请求 2.0控制器。

公开(公告)号：WO2015195612A1

公开(公告)日：2015-12-23

申请号：PCT/US2015/035948

申请日：2015-06-16

Applicant: QUALCOMM INCORPORATED

Inventor： REMPLE, Terrence, Brian ,  DANG, Nam, Van ,  SHAHROKHINIA, Sassan

IPC: G06F13/42

CPC classification number: G06F13/426 ,  G06F13/382 ,  G06F13/385 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0038 ,  G06F2213/3812

Abstract: A link layer to physical layer (PHY) serial interface is disclosed. In one aspect, a system on a chip (SoC) integrated circuit (IC) includes a link layer circuit, and a remote IC includes a Universal Serial Bus (USB) PHY circuit. A bus having four or fewer wires connects the two ICs. A link bridge communicates with the link layer circuit and serializes USB Transceiver Macrocell Interface (UTMI) signaling received from the link layer circuit as high speed (HS) USB messages for transmission to the remote IC. The link bridge also receives HS messages from the USB PHY circuit on the remote IC. The link bridge deserializes the HS messages to extract UTMI signaling and passes the extracted UTMI signaling to the link layer circuit.

Abstract translation: 公开了到物理层（PHY）串行接口的链路层。 在一个方面，一种片上系统（SoC）集成电路（IC）包括链路层电路，并且远程IC包括通用串行总线（USB）PHY电路。 具有四条或更少线的总线连接两个IC。 链路桥与链路层电路通信，并将从链路层电路接收的USB收发器宏小区接口（UTMI）信号串行化为高速（HS）USB消息，以传输到远程IC。 链路桥接器还从远程IC上的USB PHY电路接收HS消息。 链路桥接反序列化HS消息以提取UTMI信令，并将提取的UTMI信令传递到链路层电路。