Abstract:
Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply connects a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. Integration of the voltage regulator on the SoC reduces parasitic impedance be between the voltage regulator and the load to aid in reducing voltage droops. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.
Abstract:
A method for temperature mitigation includes receiving a signal from a temperature sensor that is disposed within a computing device. A processor chip within the computing device produces heat. The signal from the temperature sensor is converted to temperature data. The method further includes processing the temperature data to generate an estimate of a temperature of an external surface of the device. The processing includes applying a low pass filter to the temperature data, applying an amplitude attenuation to the temperature data, and applying a delay to the temperature data. The method further includes reducing an operating parameter of the processor chip, such as operating frequency, in response to the estimated temperature of the external surface of the device.
Abstract:
An apparatus and method are disclosed for providing efficient operation in a feedback loop having a synchronous buck converter. The synchronous buck converter includes a plurality of individually selectable phases, where each of the phases has a plurality of individually selectable and parallel switching legs. The circuit stores information that associates multiple different load values with respective configuration settings that each define a number of phases and a number of switching legs. As the load changes, the circuit measures the load and selects an appropriate configuration setting. The circuit applies the selected configuration setting to operate the number of phases and a number of parallel switching legs in the buck converter.
Abstract:
Some novel features pertain to an inductor structure that includes a first inductor winding, a second inductor winding and a filler. The first inductor winding includes an electrically conductive material. The second inductor winding includes an electrically conductive material. The filler is laterally located between the first inductor winding and the second inductor winding. The filler is configured to provide structural coupling of the first and second inductor windings. In some implementations, the first inductor winding is laterally co-planar to the second inductor winding. In some implementations, the first inductor winding has a first spiral shape and the second inductor winding has a second spiral shape. In some implementations, the first inductor winding and the second inductor winding have an elongated circular shape. In some implementations, the filler is an epoxy.
Abstract:
A semiconductor device may include a semiconductor die having an active region. The semiconductor device may also include a thermocouple mesh proximate to the active region. The thermocouple mesh may include a first set of wires of a first material extending in a first direction, and a second set of wires of a second material. The second material may be different from the first material. In addition, the second set of wires may extend in a second direction different than the first direction of the first wires.
Abstract:
An apparatus and method are disclosed for providing voltage control at a load of a buck converter. The buck converter is in a feedback loop so that a reference voltage determines a pulse width modulated (PWM) signal that is fed to the buck converter, and an output voltage of the buck converter is fed back to a PWM control circuit to maintain a value of the output voltage. The load at the buck converter provides event counters to a transient load current prediction circuit, which uses a curve fitting algorithm or other adaptive control algorithm to predict a change in current at the load. The transient load current prediction circuit then manipulates the reference voltage in accordance with the predicted change in current at the load.
Abstract:
Some implementations provide a coupled inductor structure that includes a first discrete inductor configured to generate a magnetic field, a second discrete inductor, and a first ferromagnetic layer coupled to the first discrete inductor and the second discrete inductor. The first ferromagnetic layer is configured to concentrate the magnetic field generated by the first discrete inductor within the coupled inductor structure. In some implementations, the coupled inductor structure further includes a second ferromagnetic layer coupled to the first discrete inductor and the second discrete inductor. The second ferromagnetic layer is configured to concentrate the magnetic field generated by the first discrete inductor within the coupled inductor structure. In some implementations, the coupled inductor structure is a bifilar inductor structure. The first discrete inductor includes a first set of windings and the second discrete inductor includes a second set of windings. The first and second discrete inductors share a common core.
Abstract:
A switch-mode power supply is provided that includes a comparator for producing a pulse-width modulated (PWM) controller clock signal for controlling a power switch in the switch-mode power supply. The switch-mode power supply is configured to superimpose a DC-free version of a ramp voltage with an error voltage to produce a combined voltage. The comparator compares the combined voltage to a reference voltage to produce the PWM controller clock signal.
Abstract:
Low dropout (LDO) regulators are described herein for providing regulated voltages for multiple voltage domains. In one embodiment, a voltage regulator comprises a plurality of pass transistors, each of the plurality of pass transistors being coupled between an input supply rail and a respective one of a plurality of regulator outputs. The voltage regulator also comprises a plurality of averaging resistors configured to average a plurality of feedback voltages to generate an average feedback voltage, wherein each of the plurality of feedback voltages provides voltage feedback for a respective one of the plurality of regulator outputs. The voltage regular further comprises an amplifier having a first input coupled to the average feedback voltage, and a second input coupled to a reference voltage, wherein the amplifier is configured to drive the plurality of pass transistors in a direction that reduces a difference between the reference voltage and the average feedback voltage.
Abstract:
An apparatus and method are disclosed for efficiently using power at a voltage regulator, such as a synchronous buck converter. The synchronous buck converter includes a first switch and a second switch operated by a first control signal and a second control signal, respectively, where the first and second control signals have a corresponding phase difference. A logic circuit measures a duty cycle of an input pulse width modulated (PWM) signal against iterative changes of the phase difference between the first control signal and the second control signal. The logic circuit selects a phase difference corresponding to a minimum value of the PWM signal, thereby optimizing dead time at the synchronous buck converter. The logic circuit may include a Digital Pulse Width Modulator.