公开(公告)号：WO2022191956A1

公开(公告)日：2022-09-15

申请号：PCT/US2022/016372

申请日：2022-02-15

Applicant: QUALCOMM INCORPORATED

Inventor： O'SULLIVAN, Tomas ,  LEUNG, Lai Kan ,  PAN, Dongling ,  YU, Jianjun ,  PARK, Dongmin

IPC: H04B1/06 ,  H04B1/40

Abstract: A frequency synthesizer system may include a first voltage-controlled oscillator (VCO) circuit, a second VCO circuit, and multiplexing circuitry. The multiplexing circuitry may be configured to select either the output of the first VCO circuit or the output of the second VCO circuit in response to a mode selection signal.

公开(公告)号：EP4352878A1

公开(公告)日：2024-04-17

申请号：EP22727719.1

申请日：2022-05-17

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Alvin Siu-Chi ,  O'SULLIVAN, Tomas ,  YU, Jianjun ,  TANG, Yiwu

IPC: H03L7/197 ,  H03L7/08 ,  H03L7/081 ,  H03K5/131

CPC classification number: H03L7/081 ,  H03K5/131 ,  H03K2005/0007120130101 ,  H03L7/1976

公开(公告)号：EP4305758A1

公开(公告)日：2024-01-17

申请号：EP22707568.6

申请日：2022-02-15

Applicant: QUALCOMM INCORPORATED

Inventor： O'SULLIVAN, Tomas ,  LEUNG, Lai Kan ,  PAN, Dongling ,  YU, Jianjun ,  PARK, Dongmin

IPC: H04B1/06 ,  H04B1/40

公开(公告)号：WO2023034003A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/040084

申请日：2022-08-11

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Alvin Siu-Chi ,  CHAO, Yue ,  PARK, Dongmin ,  YOON, Heui In ,  O'SULLIVAN, Tomas ,  YU, Jianjun ,  TANG, Yiwu

IPC: H03L7/08 ,  H03L7/081 ,  H03L7/197 ,  G04F10/00

Abstract: A method of quantization noise cancellation in a phase-locked loop (PLL) is provided according to certain aspects. The PLL includes a phase detector having a first input configured to receive a reference signal and a second input configured to receive a feedback signal. The method includes delaying the reference signal by a first time delay, delaying the feedback signal by a second time delay, receiving a delta-sigma modulator (DSM) error signal, and adjusting the first time delay and the second time delay in opposite directions based on the DSM error signal.

公开(公告)号：WO2022260832A1

公开(公告)日：2022-12-15

申请号：PCT/US2022/029655

申请日：2022-05-17

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Alvin Siu-Chi ,  O'SULLIVAN, Tomas ,  YU, Jianjun ,  TANG, Yiwu

IPC: H03L7/197 ,  H03L7/08 ,  H03L7/081 ,  H03K5/131

Abstract: An aspect relates to an apparatus including an input buffer including an input configured to receive an input voltage; a ramp voltage generator including an input coupled to an output of the input buffer; an evaluation circuit including an input coupled to an output of the ramp voltage generator, wherein the evaluation circuit includes a first resistor coupled in series with first field effect transistor (FET) between a first voltage rail and a second voltage rail; and an output buffer including an input coupled to a drain of the first FET and an output configured to generate an output voltage.