公开(公告)号：WO2023034003A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/040084

申请日：2022-08-11

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Alvin Siu-Chi ,  CHAO, Yue ,  PARK, Dongmin ,  YOON, Heui In ,  O'SULLIVAN, Tomas ,  YU, Jianjun ,  TANG, Yiwu

IPC: H03L7/08 ,  H03L7/081 ,  H03L7/197 ,  G04F10/00

Abstract: A method of quantization noise cancellation in a phase-locked loop (PLL) is provided according to certain aspects. The PLL includes a phase detector having a first input configured to receive a reference signal and a second input configured to receive a feedback signal. The method includes delaying the reference signal by a first time delay, delaying the feedback signal by a second time delay, receiving a delta-sigma modulator (DSM) error signal, and adjusting the first time delay and the second time delay in opposite directions based on the DSM error signal.

公开(公告)号：EP4364296A2

公开(公告)日：2024-05-08

申请号：EP22744853.7

申请日：2022-05-31

Applicant: QUALCOMM INCORPORATED

Inventor： LIM, Younghyun ,  TANG, Yiwu ,  PARK, Dongmin ,  ZHU, Yunliang ,  KESKIN, Mustafa ,  CHAO, Yue

IPC: H03K21/08 ,  H03K23/66 ,  H03L7/24 ,  H03L7/193 ,  H03L7/183

CPC classification number: H03K21/08 ,  H03K23/667 ,  H03L7/24 ,  H03L7/183 ,  H03L7/193

公开(公告)号：WO2023278083A2

公开(公告)日：2023-01-05

申请号：PCT/US2022/031632

申请日：2022-05-31

Applicant: QUALCOMM INCORPORATED

Inventor： LIM, Younghyun ,  TANG, Yiwu ,  PARK, Dongmin ,  ZHU, Yunliang ,  KESKIN, Mustafa ,  CHAO, Yue

IPC: H03K21/08 ,  H03K23/66 ,  H03L7/24 ,  H03L7/193 ,  H03L7/183 ,  H03K23/667 ,  H03L7/0995 ,  H03L7/191

Abstract: Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time in response to the input clock; and outputs a second clock from an output of one of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another, each stage includes two PMOS FETs and an NMOS FET.

公开(公告)号：WO2022046339A1

公开(公告)日：2022-03-03

申请号：PCT/US2021/043311

申请日：2021-07-27

Applicant: QUALCOMM INCORPORATED

Inventor： CHAO, Yue ,  ZANUSO, Marco ,  RANGARAJAN, Rajagopalan ,  TANG, Yiwu

IPC: H03L7/087 ,  H03L7/081 ,  H03L7/197 ,  H03L7/089 ,  H03L7/183

Abstract: An apparatus is disclosed that implements a phase-locked loop (PLL) that uses multiple error determiners as part of a feedback loop. In an example aspect, an apparatus for generating a frequency includes a PLL. The PLL includes a loop filter, a voltage-controlled oscillator (VCO), a frequency divider, and multiple error determiners. The loop filter includes a filter input node and a filter output node. The VCO includes a VCO input node and a VCO output node. The VCO input node is coupled to the filter output node. The frequency divider includes a divider input node and multiple divider output nodes. The divider input node is coupled to the VCO output node. The multiple error determiners are coupled between the multiple divider output nodes and the filter input node.