Abstract:
Reconfiguring a transceiver design using a plurality of frequency synthesizers and a plurality of carrier aggregation (CA) receiver (Rx) and transmitter (Tx) chains, the method including: connecting a first frequency synthesizer to a first CA Tx chain; connecting the plurality of frequency synthesizers to the plurality of CA Rx chains, wherein a second frequency synthesizer of the plurality of frequency synthesizers is connected as a shared synthesizer to a first CA Rx chain and a second CA Tx chain.
Abstract:
A method of quantization noise cancellation in a phase-locked loop (PLL) is provided according to certain aspects. The PLL includes a phase detector having a first input configured to receive a reference signal and a second input configured to receive a feedback signal. The method includes delaying the reference signal by a first time delay, delaying the feedback signal by a second time delay, receiving a delta-sigma modulator (DSM) error signal, and adjusting the first time delay and the second time delay in opposite directions based on the DSM error signal.
Abstract:
An aspect relates to an apparatus including an input buffer including an input configured to receive an input voltage; a ramp voltage generator including an input coupled to an output of the input buffer; an evaluation circuit including an input coupled to an output of the ramp voltage generator, wherein the evaluation circuit includes a first resistor coupled in series with first field effect transistor (FET) between a first voltage rail and a second voltage rail; and an output buffer including an input coupled to a drain of the first FET and an output configured to generate an output voltage.
Abstract:
A tunable oscillator circuit is disclosed. The tunable oscillator circuit includes an inductor/capacitor (LC) tank circuit comprising a primary inductor coupled in parallel with a first capacitor bank. The LC tank resonates to produce an oscillating voltage at a frequency. The tunable oscillator circuit also includes a 90 degree phase shift buffer coupled to the LC tank and a transconductor. The transconductor is coupled to the 90 degree phase shift buffer and a secondary inductor. The tunable oscillator circuit also includes a secondary inductor that is inductively coupled to the primary inductor and receives a gain-scaled oscillating current from the transconductor. By changing the transconductance, the gain-scaled oscillating current in the secondary inductor will change, thus the effective primary inductance and the oscillation frequency can be tuned.
Abstract:
A VCO includes a transformer-based resonator that has a first LC tank and a second LC tank. The resonator has an even resonant mode and an odd resonant mode. The VCO further includes an active transconductance network that is coupled to a two-terminal port of the first tank and is also coupled to a two-terminal port of the second tank. A first terminal of the port of the first tank is capacitively coupled to a first terminal of the port of the second tank. A second terminal of the port of the first tank is capacitively coupled to a second terminal of the port of the second tank. The active transconductance network causes the resonator to resonate in a selectable one of the even and odd resonant modes depending on a digital control signal. The VCO is fine tuned by changing the capacitances of capacitors of the tanks.
Abstract:
An assembly involves an integrated circuit die that is bonded, e.g., flip-chip bonded, to a non-semiconductor substrate by a plurality of low-resistance microbumps. In one novel aspect, at least a part of a novel high-frequency transformer is disposed in the non-semiconductor substrate where the non-semiconductor substrate is the substrate of a ball grid array (BGA) integrated circuit package. At least one of the low-resistance microbumps connects the part of the transformer in the substrate to a circuit in the integrated circuit die. At two gigahertz, the novel transformer has a coupling coefficient k of at least at least 0.4 and also has a transformer quality factor Q of at least ten. The novel transformer structure sees use in coupling differential outputs of a mixer to a single-ended input of a driver amplifier in a transmit chain of an RF transceiver within a cellular telephone.
Abstract:
A programmable varactor apparatus may include multiple binary weighted varactors controlled by multiple digital varactor bits. A programmable varactor apparatus may include a plurality of binary weighted varactors, and a control to selectively disable one or more of the plurality of binary weighted varactors to decrease an effective capacitance of the programmable varactor apparatus. A method for changing an effective capacitance of a programmable varactor apparatus may include providing a plurality of binary weighted varactors, and disabling one or more of the plurality of binary weighted varactors to decrease the effective capacitance of the programmable varactor apparatus.
Abstract:
A frequency divider functionality detection and adjustment circuit includes an auxiliary voltage controlled oscillator (VCO) coupled to a first multiplexer (MUX), a programmable divider coupled to the first MUX, a second MUX coupled to the programmable divider, a counter coupled to the second MUX, and a controller coupled to the counter, the controller configured to adjust a supply voltage provided to the programmable divider based on a measured divide ratio, NMEAS.
Abstract:
A hybrid true single-phase clock (H-TSPC) circuit includes a first logic circuit comprising non-ratio (NR) logic, a first mode switching device coupled to an output of the first logic circuit, a second logic circuit comprising ratio (R) logic, the second logic circuit configured to receive an output of the first logic circuit, a second mode switching device coupled to an output of the second logic circuit, a third logic circuit comprising non-ratio (NR) logic, the third logic circuit configured to receive an output of the second logic circuit, and a third mode switching device coupled to an output of the third logic circuit, wherein the first logic circuit, second logic circuit, and third logic circuit are configured in a ring.