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    IMPROVED POWER SUPPLY TRANSIENT PERFORMANCE (POWER INTEGRITY) FOR A PROBE CARD ASSEMBLY IN AN INTEGRATED CIRCUIT TEST ENVIRONMENT
    3.
    发明申请
    IMPROVED POWER SUPPLY TRANSIENT PERFORMANCE (POWER INTEGRITY) FOR A PROBE CARD ASSEMBLY IN AN INTEGRATED CIRCUIT TEST ENVIRONMENT 审中-公开
    用于集成电路测试环境中的探针卡组件的改进的电源瞬态性能（功率一体化）

    公开(公告)号：WO2016195766A1

    公开(公告)日：2016-12-08

    申请号：PCT/US2016/019865

    申请日：2016-02-26

    Applicant: R&D CIRCUITS, INC.

    Inventor： WARWICK, Thomas, P. ,  RUSSELL, James, V. ,  TURPUSEEMA, Dhananjaya

    IPC: G01R31/28

    CPC classification number: G01R31/2889 ,  G01R1/07378 ,  G01R31/31901 ,  G01R31/31905

    Abstract: The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application, lit each embodiment, however, the critical improvement of this disclosure is the location of the passive components used, for supply filtering/ decoupling relative to prior art. All three embodiments, require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.

    Abstract translation: 本发明基本上描述了实现针对芯片的低阻抗（过频）功率传递的三个不同实施例。 这种低阻抗到高频允许管芯以封装级速度工作，从而降低封装级别的产量损失。 每个实施例解决了每个实施例的整个晶片探针应用的略微不同的方面，然而，本公开的关键改进是所使用的无源部件的位置，用于相对于现有技术的电源滤波/去耦。 所有三个实施例都需要一种方法来将无源部件嵌入到靠近螺距平移基板的位置，或物理地嵌入螺距平移基板。

    TRACE ANYWHERE INTERCONNECT
    4.
    发明申请
    TRACE ANYWHERE INTERCONNECT 审中-公开
    跟踪任何互连

    公开(公告)号：WO2017039790A1

    公开(公告)日：2017-03-09

    申请号：PCT/US2016/038687

    申请日：2016-06-22

    Applicant: R&D CIRCUITS, INC.

    Inventor： WARWICK, Thomas, P. ,  TURPUSEEMA, Dhananjaya ,  RUSSELL, James, V.

    IPC: H01R12/00 ,  B33Y80/00 ,  H01R12/14 ,  H01R13/02 ,  H05K1/14 ,  H05K3/36 ,  H01L23/522 ,  H01L23/535

    CPC classification number: H01R12/52 ,  H01L23/522 ,  H01L23/535 ,  H05K1/185 ,  H05K3/4046 ,  H05K2201/09118 ,  H05K2201/10287

    Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side

    Abstract translation: 本发明提供了用于在两个或更多个并联电路平面上的离散点之间形成三维布线的电介质线的方法和结构。 导线可以在三维空间中自由布线，以在两个或多个并联电路平面上的两个任意定义的点之间创建最有效的路由。 将这些三维电介质线的外表面金属化，将离散导线电耦合到它们各自的离散接触点。 这些线中的两个或更多个可以彼此紧密接触，彼此电耦合以及两个或更多个离散的接触垫。 这些电耦合接触焊盘可以在结构的相对侧或同一侧上，并且所形成的金属化导线可以源于一侧并且终止于另一侧或从相同侧产生并终止

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