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    A METHOD AND AN ELECTRICAL INTERCONNECT MECHANISM
    2.
    发明公开
    A METHOD AND AN ELECTRICAL INTERCONNECT MECHANISM 审中-公开
    法，电连接结构

    公开(公告)号：EP2798702A1

    公开(公告)日：2014-11-05

    申请号：EP13777883.3

    申请日：2013-03-28

    Applicant: R&D Circuits Inc.

    Inventor： WARWICK, Thomas, P. ,  RUSSELL, James, V. ,  MCMULLIN, Dermick ,  QUICK, William

    IPC: H01R12/00

    CPC classification number: H01R13/03 ,  H01R12/52 ,  H01R13/2414 ,  H01R43/26 ,  Y10T29/49208 ,  Y10T29/4921

    Abstract: A method and an electrical interconnect mechanism in which elastomeric pins are printed onto metal retainer tabs having at least one protrusion or tab extending laterally therefrom to engage a catch or recess of the laminated housing so as to locate each of the elastomeric pins and secure them within the housing. In one embodiment a champher may be employed with a catch or recess to engagely secure a second protrusion or tab extending laterally from another side of said elastomeric pin. In another embodiment the elastomeric pin may have a solid metal ring or a slide collar around the center of the pin wherein the ring has one or two tabs for engaging the recess in the housing and if preferred also the recess of a champfer.

    A METHOD AND AN ELECTRICAL INTERCONNECT MECHANISM
    4.
    发明申请
    A METHOD AND AN ELECTRICAL INTERCONNECT MECHANISM 审中-公开
    一种方法和电气互连机制

    公开(公告)号：WO2013158162A1

    公开(公告)日：2013-10-24

    申请号：PCT/US2013/000096

    申请日：2013-03-28

    Applicant: R&D CIRCUITS, INC.

    Inventor： WARWICK, Thomas, P. ,  RUSSELL, James, V. ,  MCMULLIN, Dermick ,  QUICK, William

    IPC: H01R12/00

    CPC classification number: H01R13/03 ,  H01R12/52 ,  H01R13/2414 ,  H01R43/26 ,  Y10T29/49208 ,  Y10T29/4921

    Abstract: A method and an electrical interconnect mechanism in which elastomeric pins are printed onto metal retainer tabs having at least one protrusion or tab extending laterally therefrom to engage a catch or recess of the laminated housing so as to locate each of the elastomeric pins and secure them within the housing. In one embodiment a champher may be employed with a catch or recess to engagely secure a second protrusion or tab extending laterally from another side of said elastomeric pin. In another embodiment the elastomeric pin may have a solid metal ring or a slide collar around the center of the pin wherein the ring has one or two tabs for engaging the recess in the housing and if preferred also the recess of a champfer.

    Abstract translation: 一种方法和电互连机构，其中弹性销被印刷到具有至少一个从其横向延伸的突起或突片的金属保持器突片上，以接合层叠壳体的卡扣或凹部，以便定位每个弹性销并将其固定在 住房。 在一个实施例中，可以使用带有卡扣或凹槽的凸轮来接合地固定从所述弹性销的另一侧横向延伸的第二突起或突出部。 在另一个实施例中，弹性体销可以具有围绕销的中心的实心金属环或滑动环，其中环具有用于接合壳体中的凹部的一个或两个突出部以及冠状器的凹部。

    IMPROVED POWER SUPPLY TRANSIENT PERFORMANCE (POWER INTEGRITY) FOR A PROBE CARD ASSEMBLY IN AN INTEGRATED CIRCUIT TEST ENVIRONMENT
    5.
    发明申请
    IMPROVED POWER SUPPLY TRANSIENT PERFORMANCE (POWER INTEGRITY) FOR A PROBE CARD ASSEMBLY IN AN INTEGRATED CIRCUIT TEST ENVIRONMENT 审中-公开
    用于集成电路测试环境中的探针卡组件的改进的电源瞬态性能（功率一体化）

    公开(公告)号：WO2016195766A1

    公开(公告)日：2016-12-08

    申请号：PCT/US2016/019865

    申请日：2016-02-26

    Applicant: R&D CIRCUITS, INC.

    Inventor： WARWICK, Thomas, P. ,  RUSSELL, James, V. ,  TURPUSEEMA, Dhananjaya

    IPC: G01R31/28

    CPC classification number: G01R31/2889 ,  G01R1/07378 ,  G01R31/31901 ,  G01R31/31905

    Abstract: The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application, lit each embodiment, however, the critical improvement of this disclosure is the location of the passive components used, for supply filtering/ decoupling relative to prior art. All three embodiments, require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.

    Abstract translation: 本发明基本上描述了实现针对芯片的低阻抗（过频）功率传递的三个不同实施例。 这种低阻抗到高频允许管芯以封装级速度工作，从而降低封装级别的产量损失。 每个实施例解决了每个实施例的整个晶片探针应用的略微不同的方面，然而，本公开的关键改进是所使用的无源部件的位置，用于相对于现有技术的电源滤波/去耦。 所有三个实施例都需要一种方法来将无源部件嵌入到靠近螺距平移基板的位置，或物理地嵌入螺距平移基板。

    STRUCTURE FOR ISOLATING HIGH SPEED DIGITAL SIGNALS IN A HIGH DENSITY GRID ARRAY
    6.
    发明申请
    STRUCTURE FOR ISOLATING HIGH SPEED DIGITAL SIGNALS IN A HIGH DENSITY GRID ARRAY 审中-公开
    在高密度网格阵列中分离高速数字信号的结构

    公开(公告)号：WO2015183797A1

    公开(公告)日：2015-12-03

    申请号：PCT/US2015/032409

    申请日：2015-05-26

    Applicant: R&D CIRCUITS, INC

    Inventor： WARWICK, Thomas, P.

    IPC: H01L23/58 ,  H01L23/485 ,  H05K9/00

    CPC classification number: H01L23/5225 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/552 ,  H01L2224/16225 ,  H05K1/0222 ,  H05K1/0243 ,  H05K1/113 ,  H05K1/116 ,  H05K2201/0723 ,  H05K2201/09227 ,  H05K2201/09618 ,  H05K2201/09809 ,  H05K2201/10674 ,  H05K2203/0207

    Abstract: Due to size and cost it becomes advantageous for integrated circuit (IC) manufacturers to use "single-ended" (one signal path per unique information path) high speed signals electrical contact pins (pins transmitting digital information that connect the integrated circuit to a printed circuit hoard) with a minimum number of surrounding powers and grounds. This lower cost method, however, creates electrical interference and coupling issues known as crosstalk between two adjacent signal paths in the via structure required to electrically connect the integrated circuit to the signal paths in the printed circuit hoard. Such crosstalk, in turn, increases jitter, degrades timing, and ultimately reduces the maximum operating speed, of the circuit (performance). This disclosure presents a structure using micro-plating, micro-drilling and micro-machining methods that isolates adjacent signals by placing a metal barrier that shunts coupling currents to ground. The micro-drilling methods also reduce the length of adjacent signal paths in a specific signal routing and controlled depth drilling sequence.

    Abstract translation: 由于尺寸和成本，集成电路（IC）制造商使用“单端”（每个唯一信息路径的一个信号路径）高速信号电接触引脚（引脚将数字信息连接到印刷电路 电路囤积）与最小数量的周围的权力和理由。 然而，这种较低成本的方法产生称为串联的电干扰和耦合问题，即将集成电路电连接到印刷电路板中的信号路径所需的通孔结构中的两个相邻信号路径之间的串扰。 这种串扰又增加了抖动，降低了定时，并最终降低了电路的最大工作速度（性能）。 本公开提供了使用微电镀，微钻孔和微加工方法的结构，其通过放置将耦合电流分流到地面的金属屏障来隔离相邻信号。 微钻孔方法还可以减小特定信号路由和受控深度钻井序列中相邻信号路径的长度。

    A STRUCTURE FOR ACCEPTING A COMPONENT FOR AN EMBEDDED COMPONENT PRINTED CIRCUIT BOARD
    7.
    发明申请
    A STRUCTURE FOR ACCEPTING A COMPONENT FOR AN EMBEDDED COMPONENT PRINTED CIRCUIT BOARD 审中-公开
    嵌入式组件印刷电路板组件的结构

    公开(公告)号：WO2015168370A1

    公开(公告)日：2015-11-05

    申请号：PCT/US2015/028453

    申请日：2015-04-30

    Applicant: R&D CIRCUITS, INC

    Inventor： TURPUSEEMA, Dhanonjaya ,  WARWICK, Thomas, P. ,  SMITH, Thomas ,  RUSSELL, James, V.

    IPC: H05K3/30 ,  H05K3/46 ,  H05K3/40 ,  G06K19/077 ,  H05K1/18

    CPC classification number: H05K1/188 ,  H05K1/144 ,  H05K1/183 ,  H05K1/186 ,  H05K3/0026 ,  H05K3/0094 ,  H05K3/321 ,  H05K3/366 ,  H05K3/4655 ,  H05K3/4679 ,  H05K2201/032 ,  H05K2201/0355 ,  H05K2201/042 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09545 ,  H05K2201/09572 ,  H05K2203/0485 ,  H05K2203/063 ,  H05K2203/11 ,  Y10T29/49128 ,  Y10T29/4914

    Abstract: A method and electrical interconnect structure internal to a printed circuit board for the purposes of creating a reliable, high performing connection method between embedded component terminals, signal traces and or power/ground planes which may occupy the same vertical space as the embedded components, such as a capacitor or resistor. Further easing the assembly and reliability through the manufacturing process of said embedded component structures. In one structure castellated drilled, plated vias connect the trace or plane within the printed circuit board to the electrical terminals of the embedded component using a permanent and highly conductive attach material. In another structure, the trace or plane connect by selective side-wall plating, which surrounds the electrical terminal of the component This structure also uses a permanent and highly conductive attach material to electrically connect the component terminal to the plated side-wall and in a final embodiment the terminals are connected through a conductive attach material through a via in the z axis to a conductive pad.

    Abstract translation: 印刷电路板内部的方法和电互连结构，用于在嵌入式组件端子，信号迹线和/或电源/接地平面之间建立可靠的，高性能的连接方法，其可能占据与嵌入式组件相同的垂直空间，例如 作为电容器或电阻器。 通过所述嵌入式组件结构的制造过程进一步减轻组装和可靠性。 在一种结构化的钻孔中，电镀通孔使用永久且高度导电的附着材料将印刷电路板中的迹线或平面连接到嵌入式部件的电气端子。 在另一种结构中，轨迹或平面通过选择性侧壁电镀连接，其围绕部件的电端子。该结构还使用永久且高度导电的附着材料将部件端子电连接到电镀侧壁 最终实施例中，端子通过导电附着材料通过z轴中的通孔连接到导电垫。

    EMBEDDED ISOLATION FILTER
    8.
    发明申请
    EMBEDDED ISOLATION FILTER 审中-公开

    公开(公告)号：WO2012047266A3

    公开(公告)日：2012-04-12

    申请号：PCT/US2011/001663

    申请日：2011-09-28

    Applicant: R&D CIRCUITS, INC.

    Inventor： WARWICK, Thomas, P. ,  RUSSELL, James, V.

    IPC: H01P1/20 ,  H01P1/203 ,  H01P1/205

    Abstract: The present disclosure relates to reducing unwanted RF noise in a printed circuit board (PCB) containing an RF device. An isolation filter is embedded in a PCB containing an RDF device. By placing the isolation filter as close as possible to the RF device in order to dramatically reduce unwanted RF noise due to unavoidable coupling between Vias and planes in the PCB structure.

    TRACE ANYWHERE INTERCONNECT
    9.
    发明申请
    TRACE ANYWHERE INTERCONNECT 审中-公开
    跟踪任何互连

    公开(公告)号：WO2017039790A1

    公开(公告)日：2017-03-09

    申请号：PCT/US2016/038687

    申请日：2016-06-22

    Applicant: R&D CIRCUITS, INC.

    Inventor： WARWICK, Thomas, P. ,  TURPUSEEMA, Dhananjaya ,  RUSSELL, James, V.

    IPC: H01R12/00 ,  B33Y80/00 ,  H01R12/14 ,  H01R13/02 ,  H05K1/14 ,  H05K3/36 ,  H01L23/522 ,  H01L23/535

    CPC classification number: H01R12/52 ,  H01L23/522 ,  H01L23/535 ,  H05K1/185 ,  H05K3/4046 ,  H05K2201/09118 ,  H05K2201/10287

    Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side

    Abstract translation: 本发明提供了用于在两个或更多个并联电路平面上的离散点之间形成三维布线的电介质线的方法和结构。 导线可以在三维空间中自由布线，以在两个或多个并联电路平面上的两个任意定义的点之间创建最有效的路由。 将这些三维电介质线的外表面金属化，将离散导线电耦合到它们各自的离散接触点。 这些线中的两个或更多个可以彼此紧密接触，彼此电耦合以及两个或更多个离散的接触垫。 这些电耦合接触焊盘可以在结构的相对侧或同一侧上，并且所形成的金属化导线可以源于一侧并且终止于另一侧或从相同侧产生并终止

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