Abstract:
A vertical MOSFET in a silicon wafer having opposing major surfaces includes a source electrode on one surface, a drain electrode on the second surface, and an internally disposed insulated gate. The silicon between the insulated gate and each of the major surfaces is of first conductivity type and the silicon that is laterally adjacent to the insulated gate is of second conductivity type, such that a predetermined voltage on the insulated gate creates an inversion channel extending a predetermined distance into the laterally adjacent silicon. That portion of the laterally adjacent silicon where the inversion channel is formed is of relatively lightly doped material, whereas other areas of the laterally adjacent silicon is relatively heavily doped. The silicon that is between the insulated gate and each wafer surface includes a relatively lightly doped voltage-supporting region contiguous with the insulated gate and the laterally adjacent silicon and a relatively heavily doped region between this voltage-supporting region and the surface. Additionally, the interface between the insulated gate and the laterally adjacent silicon has a low density of interface states.
Abstract:
Glass workpieces having a conductive material film on one surface, for eventual use as substrates between which a liquid crystal material is contained, are treated to remove or deplete various impurities from a thin region within the substrates at the one surface.
Abstract:
A vertical MOSFET device includes a semiconductor wafer having source, body and drain regions of alternate conductivity type disposed therein. The source and drain regions are located so as to define the length and width of a channel region in the body region at a surface of the wafer. The body region further includes a similar conductivity type supplementary region having a relatively high areal dopant concentration. The supplementary region, which can be fabricated by ion implantation, extends laterally beneath a portion of the channel region. A source electrode is disposed on one wafer surface and a drain electrode is disposed on an opposing wafer surface.
Abstract:
An IGFET (10) with reduced parasitic bipolar effects comprises a semiconductor wafer (12) having a drain region (20, 22) of first conductivity type contiguous with a wafer surface (14). A body region (24) of second conductivity type is diffused into the wafer (12) from a portion of the wafer surface (14) so as to form a body/drain PN junction (26). A source region (28) of first conductivity type is diffused from the water surface (14) within the boundary of the body region (24) so as to form a source/body PN junction (30) which extends to a predetermined depth from the wafer surface (14). The source/body PN junction (30) is spaced from the body/drain PN junction (26) so as to define a channel region (32) in the body region (24) at the wafer surface (14). An aluminium layer (42) is formed in the wafer surface (14) such that the aluminium electrically contacts via aluminium "spikes" (43) the source/body PN junction (30) from being biased during device (10) operation.
Abstract:
A vertical MOSFET device includes a semiconductor wafer having source, body and drain regions of alternate conductivity type disposed therein. The source and drain regions are located so as to define the length and width of a channel region in the body region at a surface of the wafer. The body region further includes a similar conductivity type supplementary region having a relatively high areal dopant concentration. The supplementary region, which can be fabricated by ion implantation, extends laterally beneath a portion of the channel region. A source electrode is disposed on one wafer surface and a drain electrode is disposed on an opposing wafer surface.
Abstract:
A vertical MOSFET device includes a semiconductor wafer having source, body and drain regions of alternate conductivity type disposed therein. The source and drain regions are located so as to define the length and width of a channel region in the body region at a surface of the wafer. The body region further includes a similar conductivity type supplementary region having a relatively high areal dopant concentration. The supplementary region, which can be fabricated by ion implantation, extends laterally beneath a portion of the channel region. A source electrode is disposed on one wafer surface and a drain electrode is disposed on an opposing wafer surface.
Abstract:
Glass workpieces having a conductive material film on one surface, for eventual use as substrates between which a liquid crystal material is contained, are treated to remove or deplete various impurities from a thin region within the substrates at the one surface.
Abstract:
A vertical MOSFET device includes a semiconductor wafer having source, body and drain regions of alternate conductivity type disposed therein. The source and drain regions are located so as to define the length and width of a channel region in the body region at a surface of the wafer. The body region further includes a similar conductivity type supplementary region having a relatively high areal dopant concentration. The supplementary region, which can be fabricated by ion implantation, extends laterally beneath a portion of the channel region. A source electrode is disposed on one wafer surface and a drain electrode is disposed on an opposing wafer surface.