公开(公告)号：WO1982002637A1

公开(公告)日：1982-08-05

申请号：PCT/US1982000086

申请日：1982-01-25

Applicant: RCA CORP

Inventor： RCA CORP ,  STROLLE CHRISTOPHER HUGH ,  SMITH TERRANCE RAYMOND ,  LEWIS HENRY GARTON JR ,  ACAMPORA ALFONSE ,  REITMEIER GLENN ARTHUR

IPC: H04N05/02

CPC classification number: H04N9/78 ,  G06F1/0307 ,  G06F1/0353 ,  G06F1/0356 ,  G06F2101/04 ,  G06F2101/08 ,  G06F2101/10 ,  G06T3/00 ,  G09G5/395 ,  G11C7/00 ,  G11C8/04 ,  G11C8/16 ,  H04N9/646

Abstract: A digital memory (10) which contains digital data words representative of a desired symmetrical transfer characteristic of a digital signal processor. Digital signals which are to be processed are applied to the address inputs of the memory (10), producing output signals in conformance with the desired transfer characteristic. Advantage is taken of the symmetrical nature of the response characteristic to minimize the size of the memory. Data words corresponding to only a portion of the full dynamic range of the digital signal processor are stored in the memory (10), and memory locations are addressed and read out in accordance with the value of a polarity-determining bit of the input digital signal, with the output signals being translated over the required full dynamic range in accordance with the value of the polarity-determining bit. In a preferred embodiment of the invention, the memory (10) is a random access memory, with stored data values being altered in response to a user control to change the transfer characteristic of the processor.

Abstract translation: 数字存储器（10），其包含表示数字信号处理器的期望对称传送特性的数字数据字。 要处理的数字信号被施加到存储器（10）的地址输入端，产生符合期望传输特性的输出信号。 利用响应特性的对称性优点来最小化存储器的大小。 仅对应于数字信号处理器的全部动态范围的一部分的数据字被存储在存储器（10）中，并且根据输入数字信号的极性确定位的值来寻址和读出存储单元 ，其中输出信号根据极性确定位的值在所需的全动态范围内转换。 在本发明的优选实施例中，存储器（10）是随机存取存储器，响应于用户控制改变存储的数据值，改变处理器的传送特性。

公开(公告)号：EP0070311A4

公开(公告)日：1985-06-06

申请号：EP82900743

申请日：1982-01-25

Applicant: RCA CORP

Inventor： STROLLE CHRISTOPHER HUGH ,  SMITH TERRANCE RAYMOND ,  LEWIS HENRY GARTON JR ,  ACAMPORA ALFONSE ,  REITMEIER GLENN ARTHUR

IPC: G06F1/03 ,  G06F1/035 ,  G06T3/00 ,  G09G5/395 ,  G11C7/00 ,  G11C8/04 ,  G11C8/16 ,  H04N9/64 ,  H04N9/78 ,  H04N5/02

CPC classification number: H04N9/78 ,  G06F1/0307 ,  G06F1/0353 ,  G06F1/0356 ,  G06F2101/04 ,  G06F2101/08 ,  G06F2101/10 ,  G06T3/00 ,  G09G5/395 ,  G11C7/00 ,  G11C8/04 ,  G11C8/16 ,  H04N9/646

Abstract: A digital memory (10) which contains digital data words representative of a desired symmetrical transfer characteristic of a digital signal processor. Digital signals which are to be processed are applied to the address inputs of the memory (10), producing output signals in conformance with the desired transfer characteristic. Advantage is taken of the symmetrical nature of the response characteristic to minimize the size of the memory. Data words corresponding to only a portion of the full dynamic range of the digital signal processor are stored in the memory (10), and memory locations are addressed and read out in accordance with the value of a polarity-determining bit of the input digital signal, with the output signals being translated over the required full dynamic range in accordance with the value of the polarity-determining bit. In a preferred embodiment of the invention, the memory (10) is a random access memory, with stored data values being altered in response to a user control to change the transfer characteristic of the processor.