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    1.
    发明专利
    未知

    公开(公告)号：BE776063A

    公开(公告)日：1972-03-16

    申请号：BE776063

    申请日：1971-11-30

    Applicant: RCA CORP

    Inventor： LIMBERG A L ,  STECKLER S A

    IPC: H02H7/20 ,  H03K4/08 ,  H03K4/64 ,  H01H

    Abstract: A protection circuit limits the collector current of a transistor employed as a clamp-to-ground stage in the event the collector terminal of the transistor is accidentally short circuited during conduction to a low-impedance voltage source. The protection circuit includes a transistor which has its base-emitter junction coupled across the base-emitter junction of the clamping transistor and has a collector resistor chosen to provide a saturation current for the protection transistor which holds the base-emitter junction voltage at a level which limits the collector current of the clamping transistor.

    2.
    发明专利
    未知

    公开(公告)号：SE408117B

    公开(公告)日：1979-05-14

    申请号：SE7500673

    申请日：1975-01-22

    Applicant: RCA CORP

    Inventor： LIMBERG A L ,  STECKLER S A

    IPC: H04N5/06 ,  H04N5/04 ,  H04N5/08 ,  H04N5/12 ,  H04N5/213

    Abstract: A dual mode deflection synchronizing system includes a resettable counter which generates noise-free internal synchronizing signals and signals representative of the interval during which external vertical synchronizing signals should be received provided the counter is properly synchronized. A sync signal verification detector is coupled to the source of external vertical sync signals and to a mode switch so that if the external signals arrive during this prediction interval as determined by the sync signal verification detector the system continues to operate in a synchronized mode on its internally generated synchronizing signals. If the external signals do not arrive during this prediction interval, the mode switch switches the system into a non-synchronized mode. A vertical sync signal detector which is also coupled to the source of external sync signals and to the mode switch begins to search for an external signal which has the time duration characteristic of an authentic external synchronizing signal. Until such a signal is received, the system continues to be synchronized by internal synchronizing signals generated by the resettable counter. When such a signal is received, the vertical sync signal detector resets the counter to correct its synchronization with the received external vertical synchronizing signal and toggles the mode switch to return the system to its synchronized mode of operation.

    3.
    发明专利
    未知

    公开(公告)号：SE364421B

    公开(公告)日：1974-02-18

    申请号：SE268870

    申请日：1970-03-02

    Applicant: RCA CORP

    Inventor： LIMBERG A L

    IPC: H03F3/343 ,  H03F3/347 ,  H04N5/48

    Abstract: 1298271 Transistor amplifying circuits RCA CORPORATION 2 March 1970 [3 March 1969] 9875/70 Heading H3T The bias on a transistor amplifier having direct coupling to a signal source is rendered independent of a D.C. component in the signal from that source. The amplifier comprises transistor 10 Fig. 2, which is biased by means of resistor 32 and diode 12, which comprises a similar transistor with base and collector strapped together. The signal is applied to its base over resistor 22, from a source comprising an A.C. component 20 and D.C. component 18. The D.C. component 18 of the signal is also applied over resistor 30 which has the same value as resistor 22, to the base of a transistor 26, the collector of which is returned to the base of transistor 10: transistor 30 is biased by means of diode 28 which Comprises a similar transistor with base and collector strapped together. Since diode 28 and transistor 26 comprise similar transistors and their bases are strapped together, they pass similar collector currents so that, resistors 30, 22 being of equal value, transistor 26 provides a path for all the current flowing through resistor 22, no bias current flowing from the resistor to transistor 10. In a modification, the bias resistor 32 is omitted and the transistor 10 biased by making resistor 22 of lower value than resistor 30 (Fig. 1, not shown). In a modification, the resistors 22, 30, Fig. 3 are returned to either end of the secondary of a transformer 34, the D.C. source being connected to its centre tap and the A.C. source to the primary winding. Alternatively, two separate A.C. sources may be coupled by means of transformers between the D.C. source and resistors 22, 30 respectively. The Specification also describes the application of the invention to a video detector circuit of the type disclosed in Specification 1,298,272.

    4.
    发明专利
    未知

    公开(公告)号：SE8403378L

    公开(公告)日：1985-01-18

    申请号：SE8403378

    申请日：1984-06-25

    Applicant: RCA CORP

    Inventor： CARLSON C R ,  ARBEITER J H ,  BESSLER R F ,  ADELSON E H ,  ANDERSON C H ,  LIMBERG A L

    IPC: H04N5/14 ,  G01R23/165 ,  G01R23/167 ,  G06F3/05 ,  G06F17/10 ,  G06T11/60 ,  H03H17/02 ,  H03M7/30 ,  H04N7/26 ,  G01R23/16

    Abstract: PURPOSE: To efficiently and accurately obtain a complex signal by inserting a delay and forming information samples, simultaneously generated in each adder when signals, having time deviation in a signal group is transmitted thereby composing the composite signal in real time. CONSTITUTION: 1st input terminals of relay means 100-2 to 100-n are connected to the 1st output terminals of relay means 100-1 to (n-1) respectively. Then, sampling frequency clocks CL1 to CLn are applied to other input terminals, and other input terminals are corrected by correcting parts 345 to 349, via delays 340 to 344 and connected to adders ADD 359 to 363, respectively. For example, when a thirdly generated signal and a fourthly generated signal are combined and transmitted, it causes time deviation. Then, the 3rd signal precedented generated is delayed for a prescribed time by the delay 342 to form an information sample practically simultaneously generated in the adder 359. Thus, since the composite signal is composed only by a realtime processing, a complex signal is obtained. efficiently and accurately.

    6.
    发明专利
    未知

    公开(公告)号：SE361115B

    公开(公告)日：1973-10-15

    申请号：SE950571

    申请日：1971-07-23

    Applicant: RCA CORP

    Inventor： LIMBERG A L

    IPC: H03F1/30 ,  H03F3/347 ,  H03H11/24 ,  H03K5/02 ,  H03K19/018 ,  H02J1/00

    Abstract: 1351685 Voltage dividing apparatus R C A CORPORATION 22 July 1971 [24 July 1970] 34363/71 Heading G3X A voltage divider network produces an output which is a regulated proportion of an input voltage independent of temperature effects at semiconductor junctions. The magnitude of the output, and its stability, depend only on the ratios of resistors in the network. In the circuit shown in Fig.3, which is capable of producing at terminal 26 a voltage V o greater than one-half of the supply voltage V s , a transistor 70 is arranged in common-emitter configuration together with a transistor 72 operated in commoncollector mode. The circuit is formed on a monolithic semi-conductor chip and also includes resistors 74, 76, 78, 80. It is shown that the output at terminal 26 is stable against variations in the base-emitter characteristic voltage of the transistors if resistors 74, 76 are of equal value. The magnitude of the output then depends solely on the relative values of resistors 78, 80. Similar circuits including additional transistors or diodes are described, enabling smaller propertions of the input voltage to be obtained, Figs. 1, 2, 4 (not shown).

    7.
    发明专利
    未知

    公开(公告)号：BE766582A

    公开(公告)日：1971-09-16

    申请号：BE766582

    申请日：1971-04-30

    Applicant: RCA CORP

    Inventor： LIMBERG A L ,  STECKLER S A

    IPC: H03D13/00 ,  H04N

    Abstract: A sample-and-hold circuit employs first and second transistors of the same conductivity type, having serially coupled collector-to-emitter current paths and including a feedback path coupling the collector of the first transistor to the base of the second transistor to provide a high-input impedance and a relatively low-output impedance circuit suitable for rapid updating of a hold capacitor. The circuit samples an applied signal when the first and second transistors are keyed into conduction by keying circuit means, and holds when these transistors are biased out of conduction. The circuit is particularly suited for application as a phase comparator.

    8.
    发明专利
    未知

    公开(公告)号：SE8403378D0

    公开(公告)日：1984-06-25

    申请号：SE8403378

    申请日：1984-06-25

    Applicant: RCA CORP

    Inventor： CARLSON C R ,  ARBEITER J H ,  BESSLER R F ,  ADELSON E H ,  ANDERSON C H ,  LIMBERG A L

    IPC: H04N5/14 ,  G01R23/165 ,  G01R23/167 ,  G06F3/05 ,  G06F17/10 ,  G06T11/60 ,  H03H17/02 ,  H03M7/30 ,  H04N7/26

    Abstract: PURPOSE: To efficiently and accurately obtain a complex signal by inserting a delay and forming information samples, simultaneously generated in each adder when signals, having time deviation in a signal group is transmitted thereby composing the composite signal in real time. CONSTITUTION: 1st input terminals of relay means 100-2 to 100-n are connected to the 1st output terminals of relay means 100-1 to (n-1) respectively. Then, sampling frequency clocks CL1 to CLn are applied to other input terminals, and other input terminals are corrected by correcting parts 345 to 349, via delays 340 to 344 and connected to adders ADD 359 to 363, respectively. For example, when a thirdly generated signal and a fourthly generated signal are combined and transmitted, it causes time deviation. Then, the 3rd signal precedented generated is delayed for a prescribed time by the delay 342 to form an information sample practically simultaneously generated in the adder 359. Thus, since the composite signal is composed only by a realtime processing, a complex signal is obtained. efficiently and accurately.

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