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    Content addressable memory
    2.
    发明授权
    Content addressable memory 有权
    内容可寻址内存

    公开(公告)号：US09042148B2

    公开(公告)日：2015-05-26

    申请号：US14151606

    申请日：2014-01-09

    Applicant: Renesas Electronics Corporation

    Inventor： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

    IPC: G11C15/00 ,  G11C15/04 ,  G11C7/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22

    CPC classification number: G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

    Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

    Abstract translation: 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

    CONTENT ADDRESSABLE MEMORY
    3.
    发明申请
    CONTENT ADDRESSABLE MEMORY 有权
    内容可寻址内存

    公开(公告)号：US20140126264A1

    公开(公告)日：2014-05-08

    申请号：US14151606

    申请日：2014-01-09

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Naoya WATANABE ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

    IPC: G11C15/04

    CPC classification number: G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

    Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

    Abstract translation: 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

    Data processing system, microcontroller and semiconductor device
    5.
    发明授权
    Data processing system, microcontroller and semiconductor device 有权
    数据处理系统，微控制器和半导体器件

    公开(公告)号：US09360922B2

    公开(公告)日：2016-06-07

    申请号：US14500110

    申请日：2014-09-29

    Applicant: Renesas Electronics Corporation

    Inventor： Masaru Haraguchi ,  Isamu Hayashi ,  Hiroyuki Kawai

    IPC: G11C5/14 ,  G06F1/32

    CPC classification number: G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

    Abstract: In order to perform easily power cutoff of a device configuring a data processing system and to improve the power reduction effect at standby, the data processing system is configured with a microcontroller, a memory IC including a nonvolatile RAM array, and a power supply unit capable of controlling the power supply to the microcontroller and the memory IC, separately. When a control signal to control read and write of data to the nonvolatile RAM array is at a high level, the memory IC is enabled read and write of data to the nonvolatile RAM array. When the control signal is at a low level, the memory IC is disenabled read and write of data to the nonvolatile RAM array. The microcontroller sets the control signal at a low level, when the memory IC is shifted to a standby state by the power supply unit.

    Abstract translation: 为了简单地执行配置数据处理系统的设备的电源切断并且提高待机时的功率降低效果，数据处理系统被配置有微控制器，包括非易失性RAM阵列的存储器IC和能够提供的电源单元 分别控制到微控制器和存储器IC的电源。 当控制对非易失性RAM阵列的读写数据的控制信号处于高电平时，使存储器IC能够将数据读写到非易失性RAM阵列。 当控制信号处于低电平时，存储器IC不能读取和写入非易失性RAM阵列。 当存储器IC由电源单元转移到待机状态时，微控制器将控制信号设置在低电平。

    DATA PROCESSING SYSTEM
    6.
    发明申请
    DATA PROCESSING SYSTEM 有权
    数据处理系统

    公开(公告)号：US20150095672A1

    公开(公告)日：2015-04-02

    申请号：US14500246

    申请日：2014-09-29

    Applicant: Renesas Electronics Corporation

    Inventor： Masaru HARAGUCHI ,  Isamu Hayashi ,  Hiroyuki Kawai ,  Hideyuki Noda

    IPC: G06F1/32 ,  G06F9/50

    CPC classification number: G06F1/329 ,  G06F9/4893 ,  G06F2209/485 ,  Y02D10/24 ,  Y02D50/20

    Abstract: The data processing system has: a plurality of hardware resources each having at least one standby mode; a control part for controlling execution of a task achieved by using, of the plurality of hardware resources, predetermined ones, and a working status of each hardware resource; and a power-source part for controlling supply of a power source to each hardware resource. The control part performs the scheduling of a scheduled execution time of the task based on information for determining a timing of executing the task, and calculates a standby time of the hardware resource based on a result of the scheduling. The control part compares the standby time with a break-even time depending on the standby mode, thereby deciding whether or not to cause each hardware resource to transition to the standby mode.

    Abstract translation: 数据处理系统具有：多个硬件资源，每个具有至少一个待机模式; 用于控制通过使用所述多个硬件资源来实现的任务的预定的控制部分和每个硬件资源的工作状态; 以及用于控制向每个硬件资源供电的电源部分。 控制部基于用于确定执行任务的定时的信息来执行任务的预定执行时间的调度，并且基于调度结果来计算硬件资源的待机时间。 控制部分根据待机模式将待机时间与休止时间进行比较，从而决定是否使每个硬件资源转换到待机模式。

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