公开(公告)号：US09620214B2

公开(公告)日：2017-04-11

申请号：US14691125

申请日：2015-04-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC: G11C15/04 ,  G11C7/22 ,  G11C7/06 ,  G11C7/14 ,  G11C7/12

CPC classification number: G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

公开(公告)号：US08599639B2

公开(公告)日：2013-12-03

申请号：US13900210

申请日：2013-05-22

Applicant: Renesas Electronics Corporation

Inventor： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

IPC: G11C5/14

CPC classification number: G05F1/468 ,  G11C5/025 ,  G11C5/147

Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

公开(公告)号：US10121541B2

公开(公告)日：2018-11-06

申请号：US15228631

申请日：2016-08-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Futoshi Igaue ,  Kenji Yoshinaga ,  Naoya Watanabe ,  Mihoko Akiyama

IPC: G06F12/00 ,  G11C15/04

Abstract: The present invention makes it possible to form a circuit configuration that is capable of executing a keyword search at an increased speed while suppressing an increase in the memory capacity of a content-addressable memory. A semiconductor device according to an aspect of the present invention searches an input data string for a predesignated keyword, and includes a first content-addressable memory that stores a partial keyword corresponding to a predetermined number of data beginning with the first data of the keyword, a second content-addressable memory that stores the entirety of the keyword, and a control circuit that is coupled to the first content-addressable memory and to the second content-addressable memory. When a portion matching the partial keyword is detected in the input data string by a search in the first content-addressable memory, the second content-addressable memory executes a search on search data extracted from the input data string.

公开(公告)号：US20140126264A1

公开(公告)日：2014-05-08

申请号：US14151606

申请日：2014-01-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naoya WATANABE ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC: G11C15/04

CPC classification number: G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract translation: 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

公开(公告)号：US10747775B2

公开(公告)日：2020-08-18

申请号：US15630230

申请日：2017-06-22

Applicant: Renesas Electronics Corporation

Inventor： Kenji Yoshinaga

IPC: G06F12/00 ,  G06F16/25 ,  G06F16/951 ,  G06F16/903

Abstract: A technique is provided that reduces the number of used entries in a CAM required to store a rule.A data conversion device generates entry data which is to be compared with a search key and is stored in an associative memory that can hold three or more values. The data conversion device includes a conversion circuit for extracting a plurality of character strings from an inputted rule in accordance with a regular expression based on the regular expression and converting first and second character strings included in the character strings, respectively, into first and second bit data different from each other, and an encode circuit that compares the first bit data and the second bit data for each bit and generates entry data where each mismatch bit among a plurality of bits included in the first bit data is converted into “Don't Care” value based on a comparison result.

公开(公告)号：US09042148B2

公开(公告)日：2015-05-26

申请号：US14151606

申请日：2014-01-09

Applicant: Renesas Electronics Corporation

Inventor： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC: G11C15/00 ,  G11C15/04 ,  G11C7/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract translation: 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。