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    METHOD FOR DETERMINING THE ESD/LATCH-UP RESISTANCE OF AN INTEGRATED CIRCUIT
    6.
    发明申请
    METHOD FOR DETERMINING THE ESD/LATCH-UP RESISTANCE OF AN INTEGRATED CIRCUIT 审中-公开
    确定集成电路ESD /闩锁上拉强度的方法

    公开(公告)号：WO03052824A2

    公开(公告)日：2003-06-26

    申请号：PCT/DE0204599

    申请日：2002-12-16

    Applicant: INFINEON TECHNOLOGIES AG ,  BARGSTAEDT-FRANKE SILKE ,  ESMARK KAI ,  GOSSNER HARALD ,  RIESS PHILIPP ,  STADLER WOLFGANG ,  STREIBL MARTIN ,  WENDEL MARTIN

    Inventor： BARGSTAEDT-FRANKE SILKE ,  ESMARK KAI ,  GOSSNER HARALD ,  RIESS PHILIPP ,  STADLER WOLFGANG ,  STREIBL MARTIN ,  WENDEL MARTIN

    IPC: H01L23/544 ,  H01L23/60 ,  H01L27/00

    CPC classification number: H01L22/34 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: The invention relates to a method for determining the ESD/latch-up resistance of an integrated circuit, said method comprising the following steps: an integrated circuit (1, 2) and a test structure (N3) are simultaneously produced by means of the same process steps; electrical parameters of the test structure (N3) are measured; characteristic values are derived from the measured parameter values, said characteristic values characterising an ESD or latch-up characteristic curve associated with the integrated circuit (1, 2); and it is checked whether the characteristic values are respectively contained in a pre-determined range associated with the same. The ranges are selected in such a way that a desired ESD/latch-up resistance is achieved when the characteristic values are respectively contained in their range.

    Abstract translation: 一种用于确定集成电路的ESD /闭锁强度等，其包括以下步骤的方法：共享通过相同的工艺步骤制造集成电路（1,2）和一个测试结构（N3），在该测试结构（N3）的电气参数的测量， 从所测量的参数值，其中所述集成电路中的一个的特征值（1，2）与ESD相关联或表征闩锁的特性曲线导出特征值，并且检查所述参数是否内的分配给它们的预定范围内的每个，所述区域 被选择为使得如果特性各自在它们的范围内，则存在期望的ESD /闭锁强度。

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