公开(公告)号：US20040108559A1

公开(公告)日：2004-06-10

申请号：US10673789

申请日：2003-09-30

Applicant: Renesas Technology Corp.

Inventor： Nobuyuki Sugii ,  Kazuhiro Ohnishi ,  Katsuyoshi Washio

IPC: H01L029/76

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78648 ,  H01L29/78687 ,  H01L29/802

Abstract: With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor. Further, it is possible to fabricate a double-gate type of strained SOI transistor or to implement mixedly mounting the strained SOI transistor and a conventional silicon or SOI transistor on the same wafer. According to the invention, for example, a strained silicon layer is grown on a strain-relaxed silicon germanium layer, and subsequently, portions of the silicon germanium layer are removed, thereby constituting a channel layer in the strained silicon layer.

Abstract translation: 利用本发明，可以避免由与应变SOI晶体管的沟道接触的硅锗层引起的短沟道特性的劣化。 此外，可以制造双栅型应变SOI晶体管，或者在同一晶片上实现将应变SOI晶体管和常规硅或SOI晶体管混合安装。 根据本发明，例如，在应变松弛硅锗层上生长应变硅层，随后去除硅锗层的部分，从而在应变硅层中构成沟道层。