公开(公告)号：US20040195648A1

公开(公告)日：2004-10-07

申请号：US10732375

申请日：2003-12-11

Applicant: Renesas Technology Corp.

Inventor： Noriaki Fujiki ,  Takashi Yamashita ,  Junko Izumitani

IPC: H01L029/00

CPC classification number: H01L24/03 ,  H01L23/5258 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device includes a lower-layer substrate, a fuse above the lower-layer substrate and blown by radiation with light, a silicon oxide film on the fuse and on an exposed portion of the surface of the lower-layer substrate, and a silicon nitride film on the silicon oxide film. The portion of the silicon oxide film on the surface of the lower-layer substrate is thicker than the fuse, and the silicon oxide film has an opening opposite the fuse.

Abstract translation: 半导体器件包括下层衬底，在下层衬底上方的熔丝并用光照射，熔丝上的氧化硅膜和下层衬底的表面的暴露部分上的硅 氧化硅膜上的氮化物膜。 下层基板的表面上的氧化硅膜的部分比熔丝厚，氧化硅膜具有与保险丝相对的开口。

公开(公告)号：US20040183197A1

公开(公告)日：2004-09-23

申请号：US10603811

申请日：2003-06-26

Applicant: Renesas Technology Corp.

Inventor： Takeru Matsuoka ,  Noriaki Fujiki ,  Hiroki Takewaka

IPC: H01L029/06

CPC classification number: H01L24/05 ,  H01L23/53219 ,  H01L23/53228 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05546 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48799 ,  H01L2224/48824 ,  H01L2924/00011 ,  H01L2924/04941 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01004

Abstract: A contact (15) and a copper interconnect line (16) as an uppermost interconnect layer are buried in an interlayer insulating film (14). A pad area (17) including aluminum alloy (such as AlCu or AlSiCu) is buried in a predetermined area of the copper interconnect line (16). A gold wire (18) is bonded to the pad area (17).

Abstract translation: 作为最上层的互连层的接触（15）和铜互连线（16）被埋在层间绝缘膜（14）中。 包括铝合金（例如AlCu或AlSiCu）的焊盘区域（17）被埋在铜互连线（16）的预定区域中。 金线（18）被结合到焊盘区域（17）。