公开(公告)号：US20040195648A1

公开(公告)日：2004-10-07

申请号：US10732375

申请日：2003-12-11

Applicant: Renesas Technology Corp.

Inventor： Noriaki Fujiki ,  Takashi Yamashita ,  Junko Izumitani

IPC: H01L029/00

CPC classification number: H01L24/03 ,  H01L23/5258 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device includes a lower-layer substrate, a fuse above the lower-layer substrate and blown by radiation with light, a silicon oxide film on the fuse and on an exposed portion of the surface of the lower-layer substrate, and a silicon nitride film on the silicon oxide film. The portion of the silicon oxide film on the surface of the lower-layer substrate is thicker than the fuse, and the silicon oxide film has an opening opposite the fuse.

Abstract translation: 半导体器件包括下层衬底，在下层衬底上方的熔丝并用光照射，熔丝上的氧化硅膜和下层衬底的表面的暴露部分上的硅 氧化硅膜上的氮化物膜。 下层基板的表面上的氧化硅膜的部分比熔丝厚，氧化硅膜具有与保险丝相对的开口。

公开(公告)号：US20040188842A1

公开(公告)日：2004-09-30

申请号：US10625513

申请日：2003-07-24

Applicant: Renesas Technology Corp.

Inventor： Hiroki Takewaka ,  Takashi Yamashita

IPC: H01L023/48

CPC classification number: H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device capable of suppressing current concentration in a region where a side surface portion of a lower-level interconnect layer and a via plug which is misaligned with the lower-level interconnect layer are connected, is provided. A lower-level interconnect layer (2) including an anti-reflective film (conductive film) (2b) in a top surface portion thereof is formed on an underlying insulating film (1). An interlayer insulating film (3) is formed so as to cover the lower-level interconnect layer (2) and the underlying insulating film (1). To allow for misalignment between a via plug (4) extending from a top surface of the interlayer insulating film (3) to the lower-level interconnect layer (2) and the lower-level interconnect layer (2), a high resistance layer (5) is provided in a side surface portion of the lower-level interconnect layer (2).

Abstract translation: 提供了能够抑制下层互连层的侧面部分和与下层互连层不对准的通孔插塞的区域中的电流集中的半导体器件。 在下面的绝缘膜（1）上形成包括其顶表面部分中的抗反射膜（导电膜）（2b）的下层互连层（2）。 形成层间绝缘膜（3）以覆盖下层布线层（2）和下层绝缘膜（1）。 为了允许从层间绝缘膜（3）的顶表面延伸到下层互连层（2）和下层互连层（2）的通孔塞（4）之间的未对准，高电阻层 5）设置在下层互连层（2）的侧面部分。