公开(公告)号：US20040065744A1

公开(公告)日：2004-04-08

申请号：US10667663

申请日：2003-09-23

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Atsushi Shiraishi ,  Takayuki Tamura ,  Chiaki Kumahara ,  Shinsuke Asari

IPC: G06K019/06

CPC classification number: G11C16/3418 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/7205 ,  G06F2212/7207 ,  G11C16/349

Abstract: The present invention provides a memory card in which stored information is not lost undesirably even when an operation power source is shut down during an erasing/writing process. A nonvolatile memory has an erase table in which a free-space information flag is associated with each physical address of a memory area and an address translation table in which a physical address of a memory area is associated with each logical address. The free-space information flag indicates whether a corresponding memory area is permitted to be erased or not. A control circuit determines a memory area to which rewrite data is to be written by referring to the free-space information flag of the erase table, reflects the physical address and the logical address of the memory area to which the data is written into the address translation table, and updates the free-space information flag of the erase table. The memory area to which rewrite data is to be written is determined by referring to the free-space information flag of the erase table, and rewriting is not performed in the same memory area.

Abstract translation: 本发明提供一种存储卡，其中即使在擦除/写入处理期间操作电源被关闭时，存储信息也不会不期望地丢失。 非易失性存储器具有擦除表，其中空闲信息标志与存储区域的每个物理地址相关联，以及地址转换表，其中存储区域的物理地址与每个逻辑地址相关联。 自由空间信息标志指示是否允许擦除对应的存储区域。 控制电路通过参照擦除表的自由空间信息标志来确定要写入重写数据的存储器区域，将数据写入地址的存储区域的物理地址和逻辑地址反映 翻译表，并更新擦除表的空闲信息标志。 通过参照擦除表的自由空间信息标志确定要写入重写数据的存储区域，并且不在同一存储区域中进行重写。

公开(公告)号：US20040174742A1

公开(公告)日：2004-09-09

申请号：US10796995

申请日：2004-03-11

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Motoki Kanamori ,  Takayuki Tamura ,  Kenji Kozakai ,  Atsushi Shikata ,  Shinsuke Asari

IPC: G11C011/34

CPC classification number: G11C16/10 ,  G11C2207/229

Abstract: In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the buffer memory, data is transferred to the non-volatile memory from a bank that becomes full, a write operation is started when one unit of data to be written into the non-volatile memory at a time has been transferred and, without waiting for the data to be written, the next write data is transferred from the host CPU to a bank from which write data has been transferred.

公开(公告)号：US20040215996A1

公开(公告)日：2004-10-28

申请号：US10811898

申请日：2004-03-30

Applicant: Renesas Technology Corp.

Inventor： Motoki Kanamori ,  Kunihiro Katayama ,  Yasuhiro Nakamura ,  Satoshi Yoshida ,  Shinsuke Asari

IPC: G06F001/04

CPC classification number: G11C7/1045 ,  G06K19/077 ,  G06K19/07732 ,  G11C16/102 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012

Abstract: The invention intends to provide a memory card conforming to an HS-MMC mode in a standard of a multimedia card, while securing compatibility of both standards of the multimedia card and an SD card. In a normal MMC mode, the data is outputted at a fall edge of a clock signal. A frequency of the clock signal is about 20 MHz. When the data is outputted at the fall edge of the clock signal, data output is in time for a next clock signal. When a parameter null1null is set to a timing register provided in a host interface, the memory card is transitioned into the HS-MMC mode. In the HS-MMC mode, a clock signal frequency is increased to about 52 MHz. Here, the data is outputted at the rise edge of the clock signal, whereby the data output is brought in time for the rise edge of the next clock signal.

Abstract translation: 本发明旨在提供符合多媒体卡标准中的HS-MMC模式的存储卡，同时确保多媒体卡的标准和SD卡的兼容性。 在正常的MMC模式中，数据在时钟信号的下降沿输出。 时钟信号的频率约为20MHz。 当在时钟信号的下降沿输出数据时，下一个时钟信号的数据输出是及时的。 当将参数'1'设置为主机接口中提供的定时寄存器时，存储卡被转换到HS-MMC模式。 在HS-MMC模式下，时钟信号频率增加到大约52MHz。 这里，在时钟信号的上升沿输出数据，从而数据输出及时输出到下一个时钟信号的上升沿。

公开(公告)号：US20040177216A1

公开(公告)日：2004-09-09

申请号：US10721362

申请日：2003-11-26

Applicant: Renesas Technology Corp.

Inventor： Shinsuke Asari ,  Takayuki Tamura ,  Atsushi Shiraishi

IPC: G06F012/08

CPC classification number: G06F12/0246 ,  G11C16/102

Abstract: A nonvolatile memory has plural memory blocks, each having a plurality of sub memory blocks, and is capable of programming to a first sub memory block within a first memory block and a second sub memory block within a second memory block in parallel. The first sub memory block has a management area for storing a management information including linking information between the first sub memory block corresponding sub memory blocks of other memory blocks. A control circuit controls reading the linking information from the first sub memory block in accordance with address information, and programming to the first sub memory block in accordance with the address information and corresponding sub memory blocks by the linking information.

Abstract translation: 非易失性存储器具有多个存储块，每个存储块具有多个子存储块，并且能够并行地编程到第一存储块内的第一子存储块和第二存储块内的第二子存储块。 第一子存储块具有用于存储管理信息的管理区域，该管理信息包括第一子存储块对应的其他存储块的子存储块之间的链接信息。 控制电路根据地址信息控制从第一子存储块读取链接信息，并根据地址信息和对应的子存储块通过链接信息对第一子存储块进行编程。