公开(公告)号：EP2023393A1

公开(公告)日：2009-02-11

申请号：EP06756849.3

申请日：2006-05-31

Applicant: Renesas Technology Corp.

Inventor： TAKAURA, Norikatsu ,  MATSUI, Yuichi ,  TERAO, Motoyasu ,  FUJISAKI, Yoshihisa ,  MATSUZAKI, Nozomu ,  KUROTSUCHI, Kenzo ,  MORIKAWA, Takahiro

IPC: H01L27/105 ,  G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0004 ,  G11C8/08 ,  G11C13/0028 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

Abstract: On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge-Sb-Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge-Sb-Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.

Abstract translation: 在其中嵌入作为下电极的插头（43）的绝缘膜（41）上，由氧化钽制成的绝缘膜（51）的叠层图案，由Ge-Sb-Te制成的记录层 导入铟的硫属化合物和由钨或钨合金制成的上电极膜（53），从而形成相变存储器。 通过在记录层（52）和插塞（43）之间插入绝缘膜（51），可以实现降低相变存储器的编程电流的效果和防止记录层（52）的剥离的效果。 此外，通过使用引入了铟的Ge-Sb-Te类硫族化物作为记录层（52），绝缘膜（51）和记录层（52）之间的功函数差增大，编程 可以减小相变存储器的电压。

公开(公告)号：EP1953824A1

公开(公告)日：2008-08-06

申请号：EP06832623.0

申请日：2006-11-14

Applicant: Renesas Technology Corp.

Inventor： MORIKAWA, Takahiro ,  TERAO, Motoyasu ,  TAKAURA, Norikatsu ,  KUROTSUCHI, Kenzo

IPC: H01L27/105 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

Abstract: On the same semiconductor substrate 1, a memory cell array in which a plurality of memory elements R having a chalcogenide-material storage layer 22 storing a high-resistance state with a high electric resistance value and a low-resistance state with a low electric resistance value by a change of an atom arrangement are disposed in a matrix is formed in a memory cell region mmry, and a semiconductor integrated circuit is formed in a logic circuit region lgc. This chalcogenide-material storage layer 22 is made of a chalcogenide material containing at least either one of Ga or In of 10.5 atom% or larger to 40 atom% or smaller, Ge of 5 atom% or larger to 35 atom% or smaller, Sb of 5 atom% or larger to 25 atom% or smaller, and Te of 40 atom% or larger to 65 atom% or smaller.

Abstract translation: 在同一半导体基板1上形成有多个存储元件R，该存储元件阵列R具有存储高电阻值的高电阻状态和低电阻值的低电阻状态的硫属化物材料存储层22 通过原子排列的变化的值被排列成矩阵形成在存储单元区域中，并且半导体集成电路形成在逻辑电路区域lgc中。 该硫族化物材料存储层22由含有10.5原子％以上且40原子％以下的Ga或In中的至少一者，5原子％以上至35原子％以下的Ge，硫化锑材料 5原子％以上且25原子％以下，Te为40原子％以上且65原子％以下。