公开(公告)号：WO2013165774A1

公开(公告)日：2013-11-07

申请号：PCT/US2013/037958

申请日：2013-04-24

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： LIU, Bo ,  TSAI, Frank Wanfang ,  PARK, Jongmin ,  LI, Yan

IPC: G11C29/00 ,  G11C7/10 ,  G11C8/04

CPC classification number: G11C29/848 ,  G11C7/1036 ,  G11C8/04 ,  G11C29/78

Abstract: In a non-volatile memory circuit, techniques are presented so that bad columns can be ignored and/or replaced during memory data input and output operations. A column redundant circuit for this purpose reduces circuit size and improves performance. User data is grouped in an interleaved manner so that data belonging to consecutive logical address will be distributed into different physical locations. For example, all column data can be physically grouped into, say, 5 divisions and user data can be written into or accessed from one division after another consecutively. Each division has its own clock control. The column redundancy block can generate bad column locations' information and send it to control logic to switch the user clock to a different division clock, thereby skipping bad columns. By controlling the clocks for different columns, the user can directly access good columns without touching bad columns.

Abstract translation: 在非易失性存储器电路中，呈现技术，使得在存储器数据输入和输出操作期间可以忽略和/或替换坏列。 用于此目的的列冗余电路可减少电路尺寸并提高性能。 用户数据以交错方式分组，使得属于连续逻辑地址的数据将被分配到不同的物理位置。 例如，所有列数据可以被物理地分组到例如5个分区中，并且用户数据可以被连续地从一个分区写入或访问。 每个部门都有自己的时钟控制。 列冗余块可以产生错误的列位置信息，并将其发送到控制逻辑以将用户时钟切换到不同的分频时钟，从而跳过不良列。 通过控制不同列的时钟，用户可以直接访问好的列，而不会碰坏列。