公开(公告)号：WO2015134239A1

公开(公告)日：2015-09-11

申请号：PCT/US2015/017371

申请日：2015-02-24

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： HUYNH, Jonathan Hoang ,  CHANG, Albert I-Ming ,  PARK, Jongmin

IPC: H03K3/011 ,  H03K3/0231

CPC classification number: H03B5/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/30 ,  G11C16/32 ,  H03B5/24 ,  H03K3/011 ,  H03K3/02315 ,  H03K3/0315

Abstract: Apparatus and methods are provided for a temperature-compensated oscillator adapted to receive an input reference current. The apparatus and methods include or provide a temperature coefficient control circuit adapted to adjust the input reference current based on temperature information, wherein the temperature coefficient control circuit receives a first signal corresponding to the temperature information at a first signal node, and a second signal corresponding to a trimmed bias signal at a second signal node.

Abstract translation: 提供了适于接收输入参考电流的温度补偿振荡器的装置和方法。 该装置和方法包括或提供一种温度系数控制电路，其适于基于温度信息调整输入参考电流，其中温度系数控制电路接收与第一信号节点处的温度信息对应的第一信号，以及相应的第二信号 到第二信号节点处的修整偏置信号。

公开(公告)号：WO2013165774A1

公开(公告)日：2013-11-07

申请号：PCT/US2013/037958

申请日：2013-04-24

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： LIU, Bo ,  TSAI, Frank Wanfang ,  PARK, Jongmin ,  LI, Yan

IPC: G11C29/00 ,  G11C7/10 ,  G11C8/04

CPC classification number: G11C29/848 ,  G11C7/1036 ,  G11C8/04 ,  G11C29/78

Abstract: In a non-volatile memory circuit, techniques are presented so that bad columns can be ignored and/or replaced during memory data input and output operations. A column redundant circuit for this purpose reduces circuit size and improves performance. User data is grouped in an interleaved manner so that data belonging to consecutive logical address will be distributed into different physical locations. For example, all column data can be physically grouped into, say, 5 divisions and user data can be written into or accessed from one division after another consecutively. Each division has its own clock control. The column redundancy block can generate bad column locations' information and send it to control logic to switch the user clock to a different division clock, thereby skipping bad columns. By controlling the clocks for different columns, the user can directly access good columns without touching bad columns.

Abstract translation: 在非易失性存储器电路中，呈现技术，使得在存储器数据输入和输出操作期间可以忽略和/或替换坏列。 用于此目的的列冗余电路可减少电路尺寸并提高性能。 用户数据以交错方式分组，使得属于连续逻辑地址的数据将被分配到不同的物理位置。 例如，所有列数据可以被物理地分组到例如5个分区中，并且用户数据可以被连续地从一个分区写入或访问。 每个部门都有自己的时钟控制。 列冗余块可以产生错误的列位置信息，并将其发送到控制逻辑以将用户时钟切换到不同的分频时钟，从而跳过不良列。 通过控制不同列的时钟，用户可以直接访问好的列，而不会碰坏列。

公开(公告)号：WO2013148095A1

公开(公告)日：2013-10-03

申请号：PCT/US2013/029374

申请日：2013-03-06

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： LEE, Seungpil ,  PARK, Jongmin

IPC: G11C7/18 ,  G11C11/56

CPC classification number: G11C16/0483 ,  G11C7/18 ,  G11C11/5621 ,  G11C16/0425 ,  G11C16/0433 ,  G11C2211/5641

Abstract: A non-volatile memory array is partitioned along the column direction into first and second portions. The first portion has SLC memory cells and the second portion has MLC memory cells. The first portion acts as a fast cache memory for the second portion. The read/write operations of the first portion are further enhanced by coupling to a set of read/write circuits immediately adjacent to the first portion, while the column of each bit line is switchably cut off at the junction between the first and second portions. In this way, the RC constant of the cut off bit line is at a minimum, which translates to faster precharge of the bit line via the read/write circuits. When the second portion is operating, its access to the set of read/write circuits is accomplished by not cutting off each bit line at the junction between the first and second portions.

Abstract translation: 沿着列方向将非易失性存储器阵列分割成第一和第二部分。 第一部分具有SLC存储单元，第二部分具有MLC存储单元。 第一部分用作第二部分的快速缓存。 通过耦合到与第一部分相邻的一组读/写电路，第一部分的读/写操作进一步增强，同时每个位线的列在第一和第二部分之间的连接处可切换地切断。 以这种方式，截止位线的RC常数处于最小值，这通过读/写电路转换为更快的位线预充电。 当第二部分工作时，其通过不切断第一和第二部分之间的连接处的每个位线来实现对该组读/写电路的访问。

公开(公告)号：WO2014004395A1

公开(公告)日：2014-01-03

申请号：PCT/US2013/047382

申请日：2013-06-24

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： MUI, Man Lung ,  PARK, Jongmin ,  NGUYEN, Hao Thai ,  LEE, Seungpil

IPC: G11C7/06 ,  G11C11/56 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C7/067 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/3436

Abstract: A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches.

Abstract translation: 介绍了一种适用于非易失性存储器电路的紧凑且通用的高速读出放大器。 感测放大器电路连接到第一和第二电源电平，用于设置位线上的编程禁止电平的第一电平和用于对用于感测操作的位线进行预充电的第二电平。 在数据锁存器之外，感测放大器只能使用NMOS晶体管。 电路的布置也允许同时对位线进行放电，将感测结果传送到其他锁存器。

公开(公告)号：WO2014014654A1

公开(公告)日：2014-01-23

申请号：PCT/US2013/049047

申请日：2013-07-02

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： MUI, Man Lung ,  CHEN, Changyuan ,  KOH, Yee Lih ,  PARK, Jongmin ,  NGUYEN, Hao Thai ,  SAKHAMURI, Vamsi Krishna ,  LEE, Seungpil

IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3436

Abstract: In a programming operation that includes repeated bitscan, program, and verify steps, the bitscan steps may be hidden by performing bitscan in parallel with program preparation and program steps. The effect of a program step may be predicted from previous observation so that when a bitscan indicates that the memory cells are close to being programmed, a last programming step may be completed without subsequent verification or bitscan steps.

Abstract translation: 在包含重复位扫描，程序和验证步骤的编程操作中，位扫描步骤可能与程序准备和程序步骤并行执行位扫描隐藏。 可以从先前的观察来预测节目步骤的效果，使得当比特扫描指示存储器单元接近被编程时，最后的编程步骤可以在没有随后的验证或位扫描步骤的情况下完成。

公开(公告)号：WO2013103504A1

公开(公告)日：2013-07-11

申请号：PCT/US2012/069817

申请日：2012-12-14

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： NGUYEN, Hao Thai ,  LEE, Juan Carlos ,  LEE, Seungpil ,  MATSUMOTO, Masahide ,  PARK, Jongmin ,  MUI, Man Lung ,  WANG, Sung-En

IPC: G11C11/56 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

Abstract: In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit lines, and, optionally, the well can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit lines can be equalized to a DC level. In some cases a non-volatile memory is programmed by an alternating set of pulses, but, for at least some pulses without any intervening verify operations. After a one pulse, but before biasing the memory for the next pulse without an intervening verify, the source and bit line levels can be left to float.

Abstract translation: 在非易失性存储器件中，写入通常由交替的脉冲和验证操作组成。 在脉冲结束时，器件必须被正确偏置才能进行准确的校验，之后器件被重新偏置用于下一个脉冲。 考虑脉冲和验证阶段之间的间隔。 对于脉冲之后的间隔，但是在建立验证条件之前，可以使源极，位线和可选的阱均衡，然后在期望的DC电平进行调节。 在验证阶段之后，但是在为下一个脉冲施加偏置存储器之前，可以将源和位线均衡为直流电平。 在一些情况下，非易失性存储器通过交替的脉冲组编程，但对于至少一些没有任何中间验证操作的脉冲。 在一个脉冲之后，但是在将存储器偏置在下一个脉冲之前没有中间验证，源和位线电平可以保持浮动。

公开(公告)号：WO2013052329A1

公开(公告)日：2013-04-11

申请号：PCT/US2012/057301

申请日：2012-09-26

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： NGUYEN, Qui Vi ,  ARIKI, Takuya ,  PARK, Jongmin

IPC: G11C8/08 ,  G11C16/08

CPC classification number: G11C8/08 ,  G11C16/08 ,  G11C16/12

Abstract: A level shifter circuit is presented that can apply a negative voltage level (VBB at TrFG) to non-selected blocks while still being able to drive a high positive level (VRDEC) when selected. An exemplary embodiment presents a negative level shifter that is not susceptible to low voltage pfet breakdown. This allows for a high voltage level shifter (transfer gate) that can drive a negative level for unselected blocks and, when enabled for a selected block, can still drive a positive high voltage level. By using a pair of low voltage PMOS device (M9, M10) whose n-wells share the same level as other PMOS transistors in the design, layout area can be minimized. The gates of this pair of PMOSs (M9, M10) are connected to VSS, thereby preventing these low voltage PMOS devices from thin oxide breakdown.

Abstract translation: 提出了一种电平移位器电路，其可以在未选择的块上施加负电压电平（VBB，TrFG），同时在选择时仍能够驱动高电平（VRDEC）。 一个示例性实施例提出了不易受低电压pfet击穿影响的负电平转换器。 这允许可以为未选择的块驱动负电平的高电压电平移位器（传输门），并且当被选择的块被使能时，仍然可以驱动正的高电压电平。 通过使用一对在设计中n阱与其他PMOS晶体管具有相同电平的低电压PMOS器件（M9，M10），布局面积可以最小化。 这对PMOS（M9，M10）的栅极连接到VSS，从而防止这些低电压PMOS器件发生薄氧化物击穿。

公开(公告)号：WO2012177368A1

公开(公告)日：2012-12-27

申请号：PCT/US2012/040145

申请日：2012-05-31

Applicant: SANDISK TECHNOLOGIES INC. ,  LIU, Bo ,  PARK, Jongmin ,  CHEN, Chen ,  KUO, Tien-Chien

Inventor： LIU, Bo ,  PARK, Jongmin ,  CHEN, Chen ,  KUO, Tien-Chien

IPC: G11C29/40 ,  G11C29/44

CPC classification number: G11C29/40 ,  G11C29/44

Abstract: A circuit (150) for counting in an N-bit string (10) a number of bits M, having a first binary value includes N latch circuits in a daisy chain (100) where each latch circuit has a tag bit that controls each to be either in a no-pass or pass state. Initially the tag bits are set according to the bits of the N-bit string where the first binary value corresponds to a no-pass state. A clock signal having a pulse train is run through the daisy chain to "interrogate" any no-pass latch circuits. It races right through any pass latch circuit. However, for a no-pass latch circuit, a leading pulse while being blocked also resets after a pulse period the tag bit from "no-pass" to "pass" state to allow subsequent pulses to pass. After all no-pass latch circuits have been reset, M is given by the number of missing pulses from the pulse train.

Abstract translation: 用于以N位串（10）计数具有第一二进制值的位M的电路（150）包括菊花链（100）中的N个锁存电路，其中每个锁存电路具有一个标签位， 要么是没有通过，要么是通过状态。 最初，标签位根据N位串的位进行设置，其中第一个二进制值对应于无通状态。 具有脉冲串的时钟信号通过菊花链运行以“询问”任何无通路锁存电路。 它可以通过任何通过锁存电路进行比赛。 然而，对于无通路锁存电路，被阻塞的前导脉冲也在标签位从“无通”状态到“通过”状态的脉冲周期之后复位，以允许随后的脉冲通过。 在所有无通路锁存电路复位之后，M由脉冲序列的丢失脉冲数给出。