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    SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST
    1.
    发明申请
    SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST 审中-公开
    通过使用耐蚀材料的结构同时选择性的宽带划分

    公开(公告)号：WO2014145387A2

    公开(公告)日：2014-09-18

    申请号：PCT/US2014/030144

    申请日：2014-03-17

    Applicant: SANMINA CORPORATION

    Inventor： IKETANI, Steve ,  KERSTEN, Dale

    CPC classification number: H05K3/429 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2203/061 ,  H05K2203/0713 ,  Y10T29/49165

    Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

    Abstract translation: 提供了具有选择性地定位在第一介电层中的第一电介质层和第一电镀抗蚀剂的多层印刷电路板。 可以将第二电镀抗蚀剂选择性地定位在第一电介质层或第二电介质层中，第二电镀抗蚀剂与第一电镀抗蚀剂分离。 通孔延伸穿过第一电介质层，第一电镀抗蚀剂和第二电镀抗蚀剂。 除了沿第一电镀抗蚀剂和第二电镀抗蚀剂之间的长度之外，通孔的内表面镀有导电材料。 这形成了具有与第二通孔段电隔离的第一通路段的分隔电镀通孔。

    HOLE PLUG FOR THIN LAMINATE
    3.
    发明申请
    HOLE PLUG FOR THIN LAMINATE 审中-公开
    孔板用于薄层压板

    公开(公告)号：WO2016106428A1

    公开(公告)日：2016-06-30

    申请号：PCT/US2015/067736

    申请日：2015-12-28

    Applicant: SANMINA CORPORATION

    Inventor： IKETANI, Shinichi ,  KERSTEN, Dale

    IPC: H05K3/40 ,  H05K1/11

    CPC classification number: H05K3/429 ,  H05K3/0035 ,  H05K3/0047 ,  H05K3/0094 ,  H05K3/421 ,  H05K2203/0207 ,  H05K2203/0713 ,  H05K2203/1476

    Abstract: A method for forming a hole plug in a laminate structure is provided. A laminate structure, is formed, including at least a dielectric layer and a first conductive foil on a first side of the dielectric layer. An unpierced or blind hole is formed in the laminate structure extending toward the first conductive foil from a second side of the dielectric layer and at least partially through the dielectric layer, the hole having a hole depth to hole diameter aspect ratio of less than ten (10) to one (1). In yet another example, the hole aspect ratio may be less than one (1) to one (1). Via fill ink may then be deposited in the hole. The via fill ink is then dried and/or cured to form a hole plug.

    Abstract translation: 提供了一种形成层压结构中的孔塞的方法。 形成层压体结构，在电介质层的第一侧上至少包括介电层和第一导电箔。 在层叠结构中形成未钝化或盲孔，从电介质层的第二侧朝向第一导电箔延伸，并且至少部分地穿过电介质层，孔的孔深孔直径纵横比小于10（ 10）到一（1）。 在另一个例子中，孔长宽比可以小于一（1）至1（1）。 然后，通过填充油墨可以沉积在孔中。 然后将通孔填充油墨干燥和/或固化以形成孔塞。

    METHODS OF FORMING SEGMENTED VIAS FOR PRINTED CIRCUIT BOARDS
    5.
    发明申请
    METHODS OF FORMING SEGMENTED VIAS FOR PRINTED CIRCUIT BOARDS 审中-公开
    形成印刷电路板的分离VIAS的方法

    公开(公告)号：WO2015095401A1

    公开(公告)日：2015-06-25

    申请号：PCT/US2014/070966

    申请日：2014-12-17

    Applicant: SANMINA CORPORATION

    Inventor： IKETANI, Shinichi ,  KERSTEN, Dale

    IPC: H05K3/46

    CPC classification number: H05K3/429 ,  H05K2201/09645 ,  H05K2203/0713 ,  Y10T29/49165

    Abstract: Novel methods for forming a printed circuit board (PCB) having one or more segmented vias are provided, including improved methods of removing the catalyst after the plating process when forming a segmented via in the PCB. After the electroless plating, excess catalyst on the surface of the plating resist is removed using a catalyst remover, such as an acidic solution that includes at least nitrite or nitrite ion and halogen ion, or the catalyst remover may be an etchant for plating resist, such as alkaline permanganate compound solution or plasma gas comprising at least one of oxygen, nitrogen, argon and tetrafluoromethane, or a mixture of at least two of these gasses. After removal of the excess catalyst, electrolytic plating is then applied to the through holes and the outer layer circuit or signal traces are formed. That is, the etching of paths on the conductive foils/layers of the core structure.

    Abstract translation: 提供了一种用于形成具有一个或多个分段通孔的印刷电路板（PCB）的新方法，包括在电镀工艺之后形成分段通孔在PCB中去除催化剂的改进方法。 在化学镀后，使用催化剂去除剂，例如至少包括亚硝酸根或亚硝酸根离子和卤素离子的酸性溶液除去电镀抗蚀剂表面上的过量催化剂，或者催化剂去除剂可以是电镀抗蚀剂的蚀刻剂， 例如包括氧，氮，氩和四氟甲烷中的至少一种的碱金属高锰酸盐化合物溶液或等离子体气体，或这些气体中的至少两种的混合物。 除去过量的催化剂后，对通孔施加电解电镀，形成外层电路或信号迹线。 也就是说，蚀刻在芯结构的导电箔/层上的路径。

    SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST
    7.
    发明公开
    SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST 审中-公开
    接触孔结构的同时和选择性WIDE GAP分区使用抵抗

    公开(公告)号：EP2974569A2

    公开(公告)日：2016-01-20

    申请号：EP14763971.0

    申请日：2014-03-17

    Applicant: Sanmina Corporation

    Inventor： IKETANI, Steve ,  KERSTEN, Dale

    IPC: H05K3/46 ,  H05K3/42

    CPC classification number: H05K3/429 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2203/061 ,  H05K2203/0713 ,  Y10T29/49165

    Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

    Abstract translation: 一种多层印刷电路板，提供了具有第一电介质层和第一镀覆在第一介电层中抗蚀剂选择性地定位。 第二电镀抗蚀可以在第一电介质层或第二电介质层中选择性地定位，所述第二抗镀剂单独与所述第一抗镀剂。 通孔穿过所述第一介电层延伸，第一耐电镀抗蚀剂，并且所述第二抗镀剂。 所述通孔的内表面被镀覆有导电材料，除了沿着第一电镀之间的长度抗蚀剂和第二抗镀剂。 这形成了通过划分具有经由电气的第一段孔镀经由段的第二隔离。

    HOLE PLUG FOR THIN LAMINATE
    8.
    发明公开
    HOLE PLUG FOR THIN LAMINATE 审中-公开
    用于薄层压板的孔塞

    公开(公告)号：EP3238512A1

    公开(公告)日：2017-11-01

    申请号：EP15874375.7

    申请日：2015-12-28

    Applicant: Sanmina Corporation

    Inventor： IKETANI, Shinichi ,  KERSTEN, Dale

    IPC: H05K3/40 ,  H05K1/11

    CPC classification number: H05K3/429 ,  H05K3/0035 ,  H05K3/0047 ,  H05K3/0094 ,  H05K3/421 ,  H05K2203/0207 ,  H05K2203/0713 ,  H05K2203/1476

    Abstract: A method for forming a hole plug in a laminate structure is provided. A laminate structure, is formed, including at least a dielectric layer and a first conductive foil on a first side of the dielectric layer. An unpierced or blind hole is formed in the laminate structure extending toward the first conductive foil from a second side of the dielectric layer and at least partially through the dielectric layer, the hole having a hole depth to hole diameter aspect ratio of less than ten (10) to one (1). In yet another example, the hole aspect ratio may be less than one (1) to one (1). Via fill ink may then be deposited in the hole. The via fill ink is then dried and/or cured to form a hole plug.

    Abstract translation: 提供了一种用于在层压结构中形成孔塞的方法。 形成层压结构，其包括在介电层的第一侧上的至少介电层和第一导电箔。 在层叠结构中形成未层叠或盲孔，从电介质层的第二侧朝向第一导电箔延伸并且至少部分地穿过电介质层，孔的孔深与孔直径的纵横比小于10（ 10）到一（1）。 在又一示例中，孔纵横比可以小于一（1）至一（1）。 通孔填充墨水然后可以沉积在孔中。 然后通路填充墨水干燥和/或固化以形成孔塞。

    METHODS OF FORMING SEGMENTED VIAS FOR PRINTED CIRCUIT BOARDS
    9.
    发明公开
    METHODS OF FORMING SEGMENTED VIAS FOR PRINTED CIRCUIT BOARDS 审中-公开
    用于生产基于分段接触孔用于电路板

    公开(公告)号：EP3085212A1

    公开(公告)日：2016-10-26

    申请号：EP14871907.3

    申请日：2014-12-17

    Applicant: Sanmina Corporation

    Inventor： IKETANI, Shinichi ,  KERSTEN, Dale

    IPC: H05K3/46

    CPC classification number: H05K3/429 ,  H05K2201/09645 ,  H05K2203/0713 ,  Y10T29/49165

    Abstract: Novel methods for forming a printed circuit board (PCB) having one or more segmented vias are provided, including improved methods of removing the catalyst after the plating process when forming a segmented via in the PCB. After the electroless plating, excess catalyst on the surface of the plating resist is removed using a catalyst remover, such as an acidic solution that includes at least nitrite or nitrite ion and halogen ion, or the catalyst remover may be an etchant for plating resist, such as alkaline permanganate compound solution or plasma gas comprising at least one of oxygen, nitrogen, argon and tetrafluoromethane, or a mixture of at least two of these gasses. After removal of the excess catalyst, electrolytic plating is then applied to the through holes and the outer layer circuit or signal traces are formed. That is, the etching of paths on the conductive foils/layers of the core structure.

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