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公开(公告)号：WO2004082180A2
公开(公告)日：2004-09-23
申请号：PCT/US0306836
申请日：2003-03-06
Applicant: SANMINA SCI CORP
Inventor： GISIN FRANZ , PANOS WILLIAM , KHANDOKAR MAHAMUD
CPC classification number: G06F17/5036 , G06F17/5068 , H05K1/023 , H05K1/0237 , H05K1/115 , H05K3/0005 , H05K2203/163
Abstract: A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) or backplane is provided. The method may involve the use of the S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias within the PCB or backplane. Such process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis may be performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the sub-circuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.
Abstract translation: 提供了一种用于增强印刷电路板（PCB）或背板的高频信号完整性的方法。 该方法可以涉及使用S参数作为与迭代过程相关联的主要成本因素，以优化PCB或背板内的单个或多个通孔集合的物理尺寸和形状。 这种过程涉及将通孔组件表示为等效的集中串联导数和阻抗，以及可以执行基本电路分析以优化次级特性的RLGC子电路，例如子电路电阻的最大化，以及 /或子电路电容的最小化。 迭代过程涉及物理尺寸的改变和通孔组件的形状，使得二次特性被优化。
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公开(公告)号：AU2003225687A8
公开(公告)日：2004-09-30
申请号：AU2003225687
申请日：2003-03-06
Applicant: SANMINA SCI CORP
Inventor： GISIN FRANZ , PANOS WILLIAM , KHANDOKAR MAHAMUD
Abstract: A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) (10) or backplane is provided. The method involves the use of S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias (12) within the PCB or backplane. Such process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis is performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the sub-circuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.
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公开(公告)号：AU2003225687A1
公开(公告)日：2004-09-30
申请号：AU2003225687
申请日：2003-03-06
Applicant: SANMINA SCI CORP
Inventor： KHANDOKAR MAHAMUD , GISIN FRANZ , PANOS WILLIAM
Abstract: A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) (10) or backplane is provided. The method involves the use of S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias (12) within the PCB or backplane. Such process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis is performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the sub-circuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.
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公开(公告)号：EP1625680A4
公开(公告)日：2009-04-08
申请号：EP03816274
申请日：2003-03-06
Applicant: SANMINA SCI CORP
Inventor： GISIN FRANZ , PANOS WILLIAM , KHANDOKAR MAHAMUD
CPC classification number: G06F17/5036 , G06F17/5068 , H05K1/023 , H05K1/0237 , H05K1/115 , H05K3/0005 , H05K2203/163
Abstract: A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) (10) or backplane is provided. The method involves the use of S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias (12) within the PCB or backplane. Such process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis is performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the sub-circuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.
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