中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.023 seconds)

    SIMULTANEOUS AND SELECTIVE PARTITIONING OF VIA STRUCTURES USING PLATING RESIST
    2.
    发明申请
    SIMULTANEOUS AND SELECTIVE PARTITIONING OF VIA STRUCTURES USING PLATING RESIST 审中-公开
    通过使用耐蚀材料的结构的同时选择性分选

    公开(公告)号：WO2006094307A2

    公开(公告)日：2006-09-08

    申请号：PCT/US2006008334

    申请日：2006-03-06

    Applicant: SANMINA SCI CORP

    Inventor： DUDNIKOV GEORGE JR ,  GISIN FRANZ

    CPC classification number: H05K3/429 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/116 ,  H05K1/167 ,  H05K3/184 ,  H05K3/422 ,  H05K2201/0187 ,  H05K2201/0738 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2201/09718 ,  H05K2201/09881 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

    Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielelectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.

    Abstract translation: 公开了通过在PCB堆叠中使用电镀抗蚀剂将多个通孔结构同时分隔成电隔离部分的系统和方法。 通过在子复合结构中的一个或多个位置选择性地沉积电镀抗蚀剂来制造这种通孔结构。 具有在不同位置沉积的电镀抗蚀剂的多个亚复合结构层压以形成期望的PCB设计的PCB堆叠。 通过导电层，电介质层和电镀抗蚀剂在PCB堆叠中钻出通孔。 因此，PCB面板具有多个通孔，然后可以通过将PCB面板放置在种子池中，然后浸入无电解铜浴中而同时进行电镀。 这种分隔的通孔增加布线密度并限制通孔结构中的短截线形成。 这种分隔的通孔允许多个电信号穿过每个电隔离部分而没有彼此的干扰。

    PRINTED CIRCUIT BOARDS AND THE LIKE WITH IMPROVED SIGNAL INTEGRITY FOR DIFFERENTIAL SIGNAL PAIRS
    4.
    发明申请
    PRINTED CIRCUIT BOARDS AND THE LIKE WITH IMPROVED SIGNAL INTEGRITY FOR DIFFERENTIAL SIGNAL PAIRS 审中-公开
    印刷电路板和类似于改善信号完整性的差分信号对

    公开(公告)号：WO2007061429A3

    公开(公告)日：2007-10-04

    申请号：PCT/US2006000753

    申请日：2006-01-09

    Applicant: SANMINA SCI CORP

    Inventor： GISIN FRANZ ,  SCHROEDER GREG

    IPC: H05K1/11

    CPC classification number: H05K1/116 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09718 ,  Y10T29/49165 ,  H01L2924/00

    Abstract: A printed circuit board with improved signal integrity for one or more differential signal pairs incorporates one or more conductive regions. In an exemplary embodiment, via structures for the differential pair that interconnect signal traces are isolated from the conductive region by an antipad area around the via structures and a conductive bridge. In alternate embodiment, an antipad area around the via structures includes a bridge between the via structures. The antipad area may comprise, by way of non-limiting example, a clipped circular aperture or a modified rectangular aperture. The bridge may, by non-limiting examples, comprise a portion of the conductive region to permit impedance tailoring of the differential pair with respect to the conductive region.

    Abstract translation: 对于一个或多个差分信号对具有改进的信号完整性的印刷电路板包括一个或多个导电区域。 在示例性实施例中，将信号迹线互连的差分对的通孔结构通过通孔结构和导电桥周围的止动区与导电区隔离。 在替代实施例中，通孔结构周围的止血区域包括通孔结构之间的桥。 作为非限制性示例，止血区域可以包括夹紧的圆形孔或修改的矩形孔。 通过非限制性示例，桥可以包括导电区域的一部分，以允许差分对相对于导电区域的阻抗调整。

    METHOD FOR OPTIMIZING HIGH FREQUENCY PERFORMANCE OF VIA STRUCTURES
    6.
    发明申请
    METHOD FOR OPTIMIZING HIGH FREQUENCY PERFORMANCE OF VIA STRUCTURES 审中-公开
    优化结构高频性能的方法

    公开(公告)号：WO2004082180A2

    公开(公告)日：2004-09-23

    申请号：PCT/US0306836

    申请日：2003-03-06

    Applicant: SANMINA SCI CORP

    Inventor： GISIN FRANZ ,  PANOS WILLIAM ,  KHANDOKAR MAHAMUD

    IPC: G06F17/50 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H04J

    CPC classification number: G06F17/5036 ,  G06F17/5068 ,  H05K1/023 ,  H05K1/0237 ,  H05K1/115 ,  H05K3/0005 ,  H05K2203/163

    Abstract: A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) or backplane is provided. The method may involve the use of the S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias within the PCB or backplane. Such process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis may be performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the sub-circuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.

    Abstract translation: 提供了一种用于增强印刷电路板（PCB）或背板的高频信号完整性的方法。 该方法可以涉及使用S参数作为与迭代过程相关联的主要成本因素，以优化PCB或背板内的单个或多个通孔集合的物理尺寸和形状。 这种过程涉及将通孔组件表示为等效的集中串联导数和阻抗，以及可以执行基本电路分析以优化次级特性的RLGC子电路，例如子电路电阻的最大化，以及 /或子电路电容的最小化。 迭代过程涉及物理尺寸的改变和通孔组件的形状，使得二次特性被优化。

    Method for optimizing high frequency performance of via structures
    7.
    发明专利
    Method for optimizing high frequency performance of via structures 未知

    公开(公告)号：AU2003225687A8

    公开(公告)日：2004-09-30

    申请号：AU2003225687

    申请日：2003-03-06

    Applicant: SANMINA SCI CORP

    Inventor： GISIN FRANZ ,  PANOS WILLIAM ,  KHANDOKAR MAHAMUD

    IPC: G06F17/50 ,  G01R31/08 ,  H01L23/52 ,  H03K17/693 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K7/00

    Abstract: A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) (10) or backplane is provided. The method involves the use of S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias (12) within the PCB or backplane. Such process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis is performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the sub-circuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.

    METHOD FOR OPTIMIZING HIGH FREQUENCY PERFORMANCE OF VIA STRUCTURES
    8.
    发明专利
    METHOD FOR OPTIMIZING HIGH FREQUENCY PERFORMANCE OF VIA STRUCTURES 未知

    公开(公告)号：AU2003225687A1

    公开(公告)日：2004-09-30

    申请号：AU2003225687

    申请日：2003-03-06

    Applicant: SANMINA SCI CORP

    Inventor： KHANDOKAR MAHAMUD ,  GISIN FRANZ ,  PANOS WILLIAM

    IPC: G06F17/50 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00

    Abstract: A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) (10) or backplane is provided. The method involves the use of S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias (12) within the PCB or backplane. Such process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis is performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the sub-circuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.

    METHOD FOR OPTIMIZING HIGH FREQUENCY PERFORMANCE OF VIA STRUCTURES
    9.
    发明公开
    METHOD FOR OPTIMIZING HIGH FREQUENCY PERFORMANCE OF VIA STRUCTURES 审中-公开
    法在合理连续性结构的高频性能

    公开(公告)号：EP1625680A4

    公开(公告)日：2009-04-08

    申请号：EP03816274

    申请日：2003-03-06

    Applicant: SANMINA SCI CORP

    Inventor： GISIN FRANZ ,  PANOS WILLIAM ,  KHANDOKAR MAHAMUD

    IPC: G06F17/50 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00

    CPC classification number: G06F17/5036 ,  G06F17/5068 ,  H05K1/023 ,  H05K1/0237 ,  H05K1/115 ,  H05K3/0005 ,  H05K2203/163

    Abstract: A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) (10) or backplane is provided. The method involves the use of S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias (12) within the PCB or backplane. Such process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis is performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the sub-circuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.

Patent Agency Ranking