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    MULTIPLE MASK AND METHOD FOR PRODUCING DIFFERENTLY DOPED REGIONS
    1.
    发明申请
    MULTIPLE MASK AND METHOD FOR PRODUCING DIFFERENTLY DOPED REGIONS 审中-公开
    用于生产不同点区域的多面罩和方法

    公开(公告)号：WO2006058594A3

    公开(公告)日：2006-09-21

    申请号：PCT/EP2005011774

    申请日：2005-11-03

    Applicant: AUSTRIAMICROSYSTEMS AG ,  KNAIPP MARTIN ,  MINIXHOFER RAINER ,  SCHREMS MARTIN

    Inventor： KNAIPP MARTIN ,  MINIXHOFER RAINER ,  SCHREMS MARTIN

    IPC: H01L21/266

    CPC classification number: H01L21/266

    Abstract: The aim of the invention is to provide a method and device for producing differently doped doping regions (DG) in a substrate (S) using a single mask (DM). For this purpose, different mask regions are provided that comprise respective elongate mask openings (MO) that are differently aligned in relation to the direction in space of an oblique implantation. Between the first and the second oblique implantation the substrate is rotated, thereby opposing maximum and minimum shading in the different mask regions in the first oblique implantation and reversing the relations in the second oblique implantation once the substrate is rotated.

    Abstract translation: 用于在具有通过单个掩模（DM）的方法不同掺杂的基板（S）的制备掺杂区（DG）的建议提供不同的掩模区域中，具有相对于倾斜注入的空间方向不同的取向每个细长掩模开口（MO）。 第一和第二倾斜注入之间使基板旋转，由此在所述第一倾斜注入的最大和最小的阴影在不同掩膜区域面对和准确基板的旋转之后扭转所述第二倾斜注入的条件。

    MEMORY CELL COMPRISING A TRENCH AND METHOD FOR PRODUCTION THEREOF
    2.
    发明申请
    MEMORY CELL COMPRISING A TRENCH AND METHOD FOR PRODUCTION THEREOF 审中-公开
    根据上述制造的沟槽和方法MEMORY CELL

    公开(公告)号：WO02073694A3

    公开(公告)日：2003-02-06

    申请号：PCT/DE0200596

    申请日：2002-02-19

    Applicant: INFINEON TECHNOLOGIES AG ,  SCHREMS MARTIN ,  WEIS ROLF

    Inventor： SCHREMS MARTIN ,  WEIS ROLF

    IPC: H01L27/108 ,  H01L21/8242

    CPC classification number: H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10891

    Abstract: The invention relates to a memory cell (1), comprising a trench (3), in which a trench capacitor is arranged. Furthermore a vertical transistor is formed in the trench (3), above the trench capacitor. A barrier layer (60) is provided for the electrical connection of the conducting trench filling (10) to a lower doped region (18) of the vertical transistor. The barrier layer (60) is a diffusion barrier for doped material or impurities contained in the conducting trench filling.

    Abstract translation: 本发明涉及具有沟槽（3）的存储单元（1），其中电容器被布置严重。 此外，在沟槽（3）的严重电容器之上的垂直晶体管形成。 对于导电严重填充（10）到所述垂直晶体管的下部掺杂区（18）的电连接，阻挡层（60）被布置。 阻挡层（60）是扩散阻挡层以包含在导电严重填充掺杂剂或杂质。

    SEMICONDUCTOR DEVICE WITH A TRENCH ISOLATION AND METHOD OF MANUFACTURING TRENCHES IN A SEMICONDUCTOR BODY
    4.
    发明申请
    SEMICONDUCTOR DEVICE WITH A TRENCH ISOLATION AND METHOD OF MANUFACTURING TRENCHES IN A SEMICONDUCTOR BODY 审中-公开
    半导体器件与透镜分离器及半导体器件制造器件的方法

    公开(公告)号：WO2007144053A3

    公开(公告)日：2008-02-21

    申请号：PCT/EP2007004324

    申请日：2007-05-15

    Applicant: AUSTRIAMICROSYSTEMS AG ,  SCHREMS MARTIN ,  PARK JONG MUN

    Inventor： SCHREMS MARTIN ,  PARK JONG MUN

    IPC: H01L21/762

    CPC classification number: H01L29/7835 ,  H01L21/76229 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7816

    Abstract: As a first step a novel low cost integration method for a plurality of deep isolation trenches on the same chip is provided. The trenches have an additional n-type or p-type doped region surrounding the trench - silicon interface. Providing such variations of doping the trench interface is achieved by using implantation masking layers or doped glass films structured by a simple resist mask. By simple layout variation of the top dimension of the trench various trench depths at the same time can be ensured. Using this method, wider trenches will be deeper and smaller trenches will be shallower.

    Abstract translation: 作为第一步，提供了用于同一芯片上的多个深隔离沟槽的新型低成本积分方法。 沟槽具有围绕沟槽 - 硅界面的附加n型或p型掺杂区域。 通过使用由简单的抗蚀剂掩模构成的注入掩模层或掺杂的玻璃膜来实现掺杂沟槽界面的这种变化。 通过沟槽的顶部尺寸的简单布局变化，可以确保同时的各种沟槽深度。 使用这种方法，更宽的沟槽将越来越深，沟槽将变浅。

    METHOD FOR PRODUCING A MEMORY, COMPRISING A MEMORY CELL AND A TRENCH ISOLATION
    5.
    发明申请
    METHOD FOR PRODUCING A MEMORY, COMPRISING A MEMORY CELL AND A TRENCH ISOLATION 审中-公开
    用存储器单元和绝缘沟槽制造存储器的方法

    公开(公告)号：WO0120643A3

    公开(公告)日：2001-10-04

    申请号：PCT/DE0003154

    申请日：2000-09-11

    Applicant: INFINEON TECHNOLOGIES AG ,  SCHREMS MARTIN ,  GERNHARDT STEFAN ,  MORHARD KLAUS DIETER ,  STEGEMANN MAIK

    Inventor： SCHREMS MARTIN ,  GERNHARDT STEFAN ,  MORHARD KLAUS DIETER ,  STEGEMANN MAIK

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10861

    Abstract: The invention relates to a method for producing a memory, comprising the following steps: formation of a trench (108) in a substrate (101), formation of an isolation collar (168) in the trench (108), formation of a dielectric layer (164) in the trench (108), filling of the trench (108) with a conductive trench-fill agent (161) and formation of a transistor (110). In order to form a trench isolation (180) once the trench (108) has been filled with the conductive trench-fill agent (161), a trench cover dielectric (430) is also formed in the trench (108) and said trench cover dielectric (430) is used as an etching mask during the formation of the trench isolation (180), in such a way that said trench isolation (180) is formed in a self-aligning manner, in relation to the trench (108). As a result of this self-aligned production of the trench isolation (180), the position of the same (180) is to a great extent independent of the alignment accuracy of the photo-exposure means.

    Abstract translation: 本发明涉及一种用于制造包括以下步骤的存储器：在衬底中形成（101）的沟槽（108），在沟槽中形成的隔离环（168）（108）在沟槽中形成一个介电层（164） （108），用导电沟槽填充物（161）填充沟槽（108）并形成晶体管（110）。 此外，Grabendeckeldielektrikum（430）在沟槽（108）形成，以形成隔离沟槽（180）为一体的形成过程中，沟槽（108）与所述导电严重填充（161）的填充后的隔离沟槽（180）和所述Grabendeckeldielektrikum（430） 使用刻蚀掩模，使得隔离沟槽（180）相对于沟槽（108）自对准。 由于隔离沟槽（180）的自对准生产，隔离沟槽（180）的位置在很大程度上与光对准器精度无关。

    SEMICONDUCTOR MEMORY LOCATION COMPRISING A TRENCH CAPACITOR AND METHOD FOR THE PRODUCTION THEREOF
    7.
    发明申请
    SEMICONDUCTOR MEMORY LOCATION COMPRISING A TRENCH CAPACITOR AND METHOD FOR THE PRODUCTION THEREOF 审中-公开
    根据上述制造坟墓电容器及其方法半导体存储单元

    公开(公告)号：WO02073657A3

    公开(公告)日：2003-05-22

    申请号：PCT/DE0200788

    申请日：2002-03-05

    Applicant: INFINEON TECHNOLOGIES AG ,  GUSTIN WOLFGANG ,  GRUENING VON SCHWERIN ULRIKE ,  TEMMLER DIETMAR ,  SCHREMS MARTIN ,  RONGEN STEFAN ,  STRASSER RUDOLF

    Inventor： GUSTIN WOLFGANG ,  GRUENING VON SCHWERIN ULRIKE ,  TEMMLER DIETMAR ,  SCHREMS MARTIN ,  RONGEN STEFAN ,  STRASSER RUDOLF

    IPC: H01L27/108 ,  H01L21/8242

    CPC classification number: H01L27/10867 ,  H01L27/10873

    Abstract: According to the invention, a trench capacitor is formed inside a trench (30) that is arranged inside a substrate (20). The trench (30) is filled with a conductive trench filling (50) that serves as an inner capacitor electrode. An epitaxial layer (75) is grown on the lateral wall of the trench (30) on the substrate (20). A buried contact (60) is arranged between the conductive trench filling (50) with the second intermediate layer (65) and the epitaxially grown layer (75). A dopant out-diffusion (80), which is formed while leading out from the buried contact (60), is arranged inside the epitaxially grown layer (75). The epitaxially grown layer (75) enables the dopant out-diffusion (80) to be further removed from a selection transistor (10) located next to the trench whereby permitting the prevention of short channel effects in the selection transistor (10).

    Abstract translation: 它是在一个沟槽30，其被布置在基底20的严重电容器形成 沟槽30填充有导电填充严重50作为内部电容器电极。 在沟槽30的基板20上的侧壁，外延层75生长。 导电填充坟50与第二中间层65和外延生长层75，掩埋接触60布置之间。 在一个Dotierstoffausdiffusion 80被布置在外延生长层75，这是从所述掩埋接触60出来而形成。 通过外延生长层75，Dotierstoffausdiffusion 80进一步远离相邻排列的选择晶体管10，从而短沟道效应可以在选择晶体管10度可以避免沟槽。

    METHOD FOR PRODUCING AN INSULATION COLLAR IN A TRENCH CAPACITOR
    8.
    发明申请
    METHOD FOR PRODUCING AN INSULATION COLLAR IN A TRENCH CAPACITOR 审中-公开
    方法用于制造绝缘环的沟槽电容器

    公开(公告)号：WO0139256A3

    公开(公告)日：2002-01-17

    申请号：PCT/DE0004114

    申请日：2000-11-22

    Applicant: INFINEON TECHNOLOGIES AG ,  SCHREMS MARTIN ,  KRASEMANN ANKE ,  HAUPT MORITZ ,  STECK SABINE ,  KOEHLER DANIEL

    Inventor： SCHREMS MARTIN ,  KRASEMANN ANKE ,  HAUPT MORITZ ,  STECK SABINE ,  KOEHLER DANIEL

    IPC: H01L21/334 ,  H01L21/8242

    CPC classification number: H01L27/10861 ,  H01L29/66181

    Abstract: The invention relates to a method for producing a trench capacitor. According to said method, after the trench has been formed, an insulating layer (35) is first deposited, from which the insulation collar (75) is subsequently to be formed. The trench (10) is then partially filled with a sacrificial fill material (40) and a thin structural layer (55) is deposited thereon. Spacers are formed from said layer which cover the insulating layer (35) in the upper region (45) of the trench (10). The sacrificial fill material (40) and the insulating layer (35) are then removed completely in the lower region (50) of the trench (10). The insulation collar (75) is thus formed in the upper region (45) of the trench (10).

    Abstract translation: 它提出了一种用于产生严重电容器的方法是在其中将要形成，首先形成沟槽形成绝缘层（35）之后，从所述绝缘环（75）被沉积的后面。 此后，该沟槽（10）与牺牲填充材料（40）被部分地填充，然后图案化的薄层（55）被沉积。 从这些间隔物所形成的覆盖在沟槽（10）的上部区域（45）的绝缘层（35）。 随后，在牺牲填充材料（40）和在所述沟槽（10）的下部区域（50）的绝缘层（35）被完全去除。 这导致绝缘卡圈（75）的沟槽（10）的上部区域（45）。

    MEMORY WITH A TRENCH CAPACITOR AND A SELECTION TRANSISTOR AND METHOD FOR PRODUCING THE SAME
    9.
    发明申请
    MEMORY WITH A TRENCH CAPACITOR AND A SELECTION TRANSISTOR AND METHOD FOR PRODUCING THE SAME 审中-公开
    具有集群电容器和选择晶体管的存储器及其制造方法

    公开(公告)号：WO0117019A3

    公开(公告)日：2001-05-10

    申请号：PCT/DE0002866

    申请日：2000-08-23

    Applicant: INFINEON TECHNOLOGIES AG ,  TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

    Inventor： TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10861 ,  H01L27/10832

    Abstract: The invention comprises a memory with a storage cell (100) that is formed in a substrate (105) and consists of a trench capacitor (110) and a transistor (160). The trench capacitor (110) is connected to the transistor (160) with a self-aligned connection (220). The transistor (160) at least partially covers said trench capacitor (110). The trench capacitor (110) is filled with a conductive trench filling and an insulating cover layer (135) is located on said conductive trench filling (130). An epitaxy layer (245) is located above said insulating cover layer (135). The transistor (160) is formed in said epitaxy layer (245). The self-aligned connection (220) is formed in a contact trench (205) and consists of an insulation collar (235) into which a conductive material (225) is introduced. A conductive cap (230) is formed on said conductive material.

    Abstract translation: 本发明包括具有存储单元（100）的存储器，存储单元（100）形成在衬底（105）中并由沟槽电容器（110）和晶体管（160）组成。 沟槽电容器（110）通过自对准端子（220）连接到晶体管（160）。 晶体管（160）至少部分地覆盖沟槽电容器（110）。 沟槽电容器（110）填充有导电沟槽填充物（130），并且在导电沟槽填充物（130）上是绝缘覆盖层（135）。 绝缘覆盖层（135）之上是外延层（245）。 晶体管（160）形成在外延层（245）中。 自对准端子（220）形成在接触沟槽（205）中并且由其中引入导电材料（225）的绝缘轴环（235）组成。 在导电材料上形成导电帽（230）。

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