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公开(公告)号：US6434056B2
公开(公告)日：2002-08-13
申请号：US74647300
申请日：2000-12-21
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： BRIGATI ALESSANDRO , DEVIN JEAN , LECONTE BRUNO
Abstract: Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided with time delay circuits whose role is to maintain the read or write operation of one microcontroller when another is selected.
Abstract translation: 两种不同类型的存储器集成在相同类型的集成电路上。 微控制器与这些存储器中的每一个相关联。 为了确保这些微控制器的操作的独立性，它们各自被提供有时间延迟电路，其作用是在选择另一个微控制器时保持一个微控制器的读取或写入操作。
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公开(公告)号：US6279068B2
公开(公告)日：2001-08-21
申请号：US74647200
申请日：2000-12-21
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： BRIGATI ALESSANDRO , DEVIN JEAN , LECONTE BRUNO
Abstract: Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided with time delay circuits whose role is to maintain the read or write operation of one microcontroller when another is selected.
Abstract translation: 两种不同类型的存储器集成在相同类型的集成电路上。 微控制器与这些存储器中的每一个相关联。 为了确保这些微控制器的操作的独立性，它们各自被提供有时间延迟电路，其作用是在选择另一个微控制器时保持一个微控制器的读取或写入操作。
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公开(公告)号：FR2758645B1
公开(公告)日：2001-12-14
申请号：FR9700642
申请日：1997-01-22
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： DEVIN JEAN , BRIGATI ALESSANDRO , LECOMTE BRUNO
IPC: G11C16/02 , G11C16/10 , G11C16/12 , G11C11/406
Abstract: In a device for programming EPROM-Flash type memory cells of memory words of a memory, a bit line of a memory cell of a given rank of the first word and at least one bit line of a memory cell of the same rank in a word that is horizontally adjacent to this first word are connected together to two common programming connections by means of a bias circuit, and the bias circuit comprises two bias voltage inputs and one bias voltage output. The programming method consists in the successive programming, during different programming cycles, of the different cells of this first word and, during the same programming cycle, a different cell, of the same rank, in at least one word that is different from this first word is programmed.
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公开(公告)号：DE69600264D1
公开(公告)日：1998-06-04
申请号：DE69600264
申请日：1996-06-17
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： GUEDJ MARC , BRIGATI ALESSANDRO , AULAS MAXENCE , DEMANGE NICOLAS
IPC: G11C11/407 , G05F3/20 , G11C16/06 , G11C17/00 , H02M3/07
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公开(公告)号：DE69502169D1
公开(公告)日：1998-05-28
申请号：DE69502169
申请日：1995-12-14
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： AULAS MAXENCE , BRIGATI ALESSANDRO , DEMANGE NICOLAS , GUEDJ MARC
Abstract: The method involves writing a word in a gp. of memory cells, selected in a line of the memory, a particular sequence is followed. Line memory cell state and values of different reference (Vref, VRH, VRB) are read. Then these readings are verified with different reference values. If no agreement is found for at least one cell of a word, this is rewritten. The desired word is written in the selected gp. of cells. Cell state reading may comprise a comparison of voltage or current of the cell with a reference, having a central (Vref), auxiliary (VRH), greater than the central, or another auxiliary (VRB), less than the central value. A word with central reference value may have its value stored in a register (REG).
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Patent Agency Ranking
公开(公告)号：FR2735896A1
公开(公告)日：1996-12-27
申请号：FR9507622
申请日：1995-06-21
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： GUEDJ MARC , BRIGATI ALESSANDRO , AULAS MAXENCE , DEMANGE NICOLAS
IPC: G11C17/00 , G11C16/04 , G11C16/14 , G11C16/02 , G11C11/407
Abstract: The EEPROM includes N word lines (WL) and M bit lines (BL) in a matrix. Cells of the same group are connected to the same word line and to K distinct bit lines. First selection lines (SL1) and command lines (CL) associated with the cell groups carry selection potentials (VPP, VCC, HVH, GND) and programming and erasing or reading controls (VPP, HVN, VREAD). A p-type group selection transistor (TSG1) connects on its channel the gates of the floating gate transistors (TGF1-TGFK) of one cell group to one of the control lines. The control gate of the selection transistor is connected to one of the selection lines when the programmer wishes to program, erase or read the contents of the first group.
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公开(公告)号：FR2735885A1
公开(公告)日：1996-12-27
申请号：FR9507619
申请日：1995-06-21
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： GUEDJ MARC , BRIGATI ALESSANDRO , AULAS MAXENCE , DEMANGE NICOLAS
Abstract: The generator includes an oscillator (3) which generates a clock signal (OSC) applied to a phase generator (2). The four outputs from the generator (ABCD) are applied to a bank of series capacitors (1) which generate a negative voltage. The generator is provided with a limiting circuit (4) which receives the negative voltage on an input (5) and generates a logic signal (ON) function of the voltage value. The circuit includes a comparator and a capacitor bridge which compares the voltage value with a reference value.
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公开(公告)号：DE69600302T2
公开(公告)日：1998-09-10
申请号：DE69600302
申请日：1996-06-17
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： GUEDJ MARC , BRIGATI ALESSANDRO , AULAS MAXENCE , DEMANGE NICOLAS
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公开(公告)号：DE69502169T2
公开(公告)日：1998-08-13
申请号：DE69502169
申请日：1995-12-14
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： AULAS MAXENCE , BRIGATI ALESSANDRO , DEMANGE NICOLAS , GUEDJ MARC
Abstract: The method involves writing a word in a gp. of memory cells, selected in a line of the memory, a particular sequence is followed. Line memory cell state and values of different reference (Vref, VRH, VRB) are read. Then these readings are verified with different reference values. If no agreement is found for at least one cell of a word, this is rewritten. The desired word is written in the selected gp. of cells. Cell state reading may comprise a comparison of voltage or current of the cell with a reference, having a central (Vref), auxiliary (VRH), greater than the central, or another auxiliary (VRB), less than the central value. A word with central reference value may have its value stored in a register (REG).
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公开(公告)号：FR2758644A1
公开(公告)日：1998-07-24
申请号：FR9700710
申请日：1997-01-21
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： DEVIN JEAN , BRIGATI ALESSANDRO , LECONTE BRUNO
Abstract: The circuit includes a detection module (1) and two timing circuits (3,4). The first timing circuit receives an initialisation signal (init) and a page writing signal (ECRP). It generates at its output a bit signal which indicates whether the timing operation has finished. The second timing circuit (4) is connected to the first circuit while its output controls the memory page writing.
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