公开(公告)号：US6434056B2

公开(公告)日：2002-08-13

申请号：US74647300

申请日：2000-12-21

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： BRIGATI ALESSANDRO ,  DEVIN JEAN ,  LECONTE BRUNO

IPC: G11C16/02 ,  G06F12/06 ,  G11C7/00 ,  G11C8/12

CPC classification number: G11C8/12 ,  G11C7/00

Abstract: Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided with time delay circuits whose role is to maintain the read or write operation of one microcontroller when another is selected.

Abstract translation: 两种不同类型的存储器集成在相同类型的集成电路上。 微控制器与这些存储器中的每一个相关联。 为了确保这些微控制器的操作的独立性，它们各自被提供有时间延迟电路，其作用是在选择另一个微控制器时保持一个微控制器的读取或写入操作。

公开(公告)号：US6279068B2

公开(公告)日：2001-08-21

申请号：US74647200

申请日：2000-12-21

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： BRIGATI ALESSANDRO ,  DEVIN JEAN ,  LECONTE BRUNO

IPC: G11C16/02 ,  G06F12/06 ,  G11C7/00 ,  G11C8/12 ,  G06F12/00

CPC classification number: G11C8/12 ,  G11C7/00

Abstract: Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided with time delay circuits whose role is to maintain the read or write operation of one microcontroller when another is selected.

Abstract translation: 两种不同类型的存储器集成在相同类型的集成电路上。 微控制器与这些存储器中的每一个相关联。 为了确保这些微控制器的操作的独立性，它们各自被提供有时间延迟电路，其作用是在选择另一个微控制器时保持一个微控制器的读取或写入操作。

公开(公告)号：FR2623651A1

公开(公告)日：1989-05-26

申请号：FR8716063

申请日：1987-11-20

Applicant: SGS THOMSON MICROELECTRONICS ,  SGS THOMSON MICROELECTRONICS SA

Inventor： DEVIN JEAN ,  JEAN DEVIN LAURENT SOURGEN ET GILLE ,  GILLE ,  SOURGEN LAURENT

IPC: G11C11/00 ,  G11C16/04 ,  G11C14/00 ,  G11C16/06 ,  G11C16/10 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: Pour éviter une différenciation technologique entre des cellules mémoires vives et des cellules mémoires mortes d'un même plan mémoire on réalise toutes les cellules mémoires en une même technologie. Ces cellules mémoires sont alors composées essentiellement de transistors à grille flottante. La programmation des cellules mémoires vives se fait, classiquement, par injection ou non de charges électroniques dans les grilles flottantes des transistors. La programmation IM, Im ou non des cellules mémoires mortes se fait par implantation d'impuretés DELTAI dans les canaux de conduction des transistors à grille flottante de ces cellules mémoires. On montre qu'on améliore la dissimulation du contenu destiné à rester cacher des cellules mémoires mortes, tout en améliorant les conditions de réalisation de prototypes à la demande.

公开(公告)号：FR2761191B1

公开(公告)日：1999-06-25

申请号：FR9703578

申请日：1997-03-20

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： DEVIN JEAN ,  LECONTE BRUNO ,  BRIGATI ALESSANDRO

IPC: G11C16/28 ,  G11C16/34 ,  G11C29/50 ,  G11C16/06

Abstract: An electrically programmable non-volatile memory organized in n-bit words includes a generator circuit to produce a verification voltage to perform a verification of a word in the memory. The generator circuit adjusts the verification voltage as a function of an information element that corresponds to the word to be verified.

公开(公告)号：FR2761802B1

公开(公告)日：1999-06-18

申请号：FR9704285

申请日：1997-04-08

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： DEVIN JEAN ,  BRIGATI ALESSANDRO ,  LECONTE BRUNO

IPC: G11C16/02 ,  G06F12/06 ,  G11C7/00 ,  G11C8/12

Abstract: The IC (1) has two memories (2,3) each controlled by a microprocessor (4,6). Each microcontroller has a circuit (13,14) executing the memory read or write operation. The read or write operations are carried out independent of the selected signal (SS1,SS2). A selection circuit (5) allows one of the memory circuits to be selected.

公开(公告)号：FR2758644B1

公开(公告)日：1999-04-09

申请号：FR9700710

申请日：1997-01-21

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： DEVIN JEAN ,  BRIGATI ALESSANDRO ,  LECONTE BRUNO

IPC: G11C16/10 ,  G11C16/32 ,  G11C7/00 ,  G11C16/02

Abstract: A circuit for activating page-write operations in a floating-gate memory includes a first and a second time lag circuit. A resetting signal resets a first time lag whenever a word is written in a buffer of the memory. The first time lag circuit provides a state bit indicating that the first time lag has ended or not ended. The second time lag circuit activates a second time lag at the end of the first time lag and the end of the second time lag activates the writing of the page in the memory. The invention also relates to a method of writing in memory that uses a first and a second time lag.

公开(公告)号：FR2756410B1

公开(公告)日：1999-01-15

申请号：FR9614776

申请日：1996-11-28

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： BRIGATI ALESSANDRO ,  LECONTE BRUNO ,  DEVIN JEAN

IPC: G11C16/10 ,  G11C16/22 ,  G11C16/06

Abstract: The page protection mechanism has pages of information temporarily held in a store (6). A processor unit (9) successively addresses the memory matrix columns (5) in the temporary store. At the end of the writing process an end of writing signal (OVR) is sent, using a comparator (10) and processor unit (11) which signals the end of the write process with an indicator (SEL), indicating the need to add a protection bit (SDP).

公开(公告)号：FR2758645A1

公开(公告)日：1998-07-24

申请号：FR9700642

申请日：1997-01-22

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： DEVIN JEAN ,  BRIGATI ALESSANDRO ,  LECOMTE BRUNO

IPC: G11C16/02 ,  G11C16/10 ,  G11C16/12 ,  G11C11/406

Abstract: The invention concerns a method for programming an EPROM-flash type memory (1) comprising memory cell words arranged in rows (23) and in columns (31), in which a transistor with floating grid (7) acts as memorising means, the floating grid transistors of memory cells (2-9) of the same word (10) having their control grid linked to a common word line connection (30) and their source connected to a common main electrode (29) of a selecting transistor (26) of which the other main electrode (28) is connected to a vertical word source connection (25). The method is characterised in that during the same programming cycle, M cell memories (2, 2b) are simultaneously programmed in N different words (10, 200), where M is less than the number P of a word memory cells, and where, M, N, and P are whole numbers.

公开(公告)号：FR2756410A1

公开(公告)日：1998-05-29

申请号：FR9614776

申请日：1996-11-28

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： BRIGATI ALESSANDRO ,  LECONTE BRUNO ,  DEVIN JEAN

IPC: G11C16/10 ,  G11C16/22 ,  G11C16/06

Abstract: The page protection mechanism has pages of information temporarily held in a store (6). A processor unit (9) successively addresses the memory matrix columns (5) in the temporary store. At the end of the writing process an end of writing signal (OVR) is sent, using a comparator (10) and processor unit (11) which signals the end of the write process with an indicator (SEL), indicating the need to add a protection bit (SDP).

公开(公告)号：FR2755286A1

公开(公告)日：1998-04-30

申请号：FR9613080

申请日：1996-10-25

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： DEVIN JEAN

IPC: G11C7/14 ,  G11C11/409 ,  G11C16/06

Abstract: The EPROM memory includes a number of cells (7) each including a floating gate transistor. The cells are connected to bit lines (8-10) and word lines (11-14) to define an array controlled by a control gate (5) connected to a word line (11). An address signal (ADR) is transmitted to a decoder (16,17) which selects the cell to be read. Reading circuits (18-20) are connected to the end of the bit lines (8-10). The connection is made only to the bit line selected by the decoder. A supplementary bit line (22) is connected to additional memory cells (23-26) which include only simple transistors. The supplementary bit line is connected to a reading circuit (27) via a transistor (29).