公开(公告)号：JP2588058B2

公开(公告)日：1997-03-05

申请号：JP29219690

申请日：1990-10-31

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CAPPELLETTI PAOLO ,  CORDA GIUSEPPE ,  GHEZZI PAOLO ,  RIVA CARLO ,  VAJANA BRUNO

IPC: G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866

公开(公告)号：JPH03225875A

公开(公告)日：1991-10-04

申请号：JP29219690

申请日：1990-10-31

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CAPPELLETTI PAOLO ,  CORDA GIUSEPPE ,  GHEZZI PAOLO ,  RIVA CARLO ,  VAJANA BRUNO

IPC: G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866

Abstract: PURPOSE: To manufacture a component which controls and stabilizes a programming voltage by a method, wherein the N-channel and P-channel transistor of a corresponding control circuit device are formed in a following manufacturing process. CONSTITUTION: An N-type sink 2 is formed on a single-crystal silicon substrate 1, and an active region 14 is formed on the surface of the sink 2. An N -dopant 4 is implanted in the surface region of the sink 2 inside the active region 14, and a gate oxide layer 5 is grown on the N -dopant region. An N -region 6 is implanted inside the N -region 4, a P -region 7 is implanted at a position located sideways off the N -region 6, and an outer node 8 (13) is formed for the N and P -regions, 6 (9) and 7 (12). By this setup, a component for limiting a programming voltage and stabilizing it with a cut-off voltage which is temporarily stable and temperature-independent can be obtained.

公开(公告)号：DE69025854T2

公开(公告)日：1996-08-01

申请号：DE69025854

申请日：1990-10-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CAPPELLETTI PAOLO ,  CORDA GIUSEPPE ,  GHEZZI PAOLO ,  RIVA CARLO ,  VAJANA BRUNO

IPC: G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866 ,  H01L21/82 ,  H01L27/02 ,  G11C16/04

Abstract: The manufacturing process comprises a first step of formation of an N type sink (2) on a single-crystal silicon substrate (1), a second step of formation of an active area (14) on the surface of said sink (2), a third step of implantation of N- dopant in a surface region (4) of the sink (2) inside said active area (14), a fourth step of growth of a layer (5) of gate oxide over said region with N- dopant, a fifth step of N+ implantation (6; 9) inside said N- region, a sixth step of P+ implantation (7; 12) in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts (8, 18; 13, 23, 33) for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.

公开(公告)号：DE3666645D1

公开(公告)日：1989-11-30

申请号：DE3666645

申请日：1986-05-27

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CAPPELLETTI PAOLO ,  TOSI MARINA

IPC: H01L21/265 ,  H01L29/10 ,  H01L29/78

公开(公告)号：IT1237666B

公开(公告)日：1993-06-15

申请号：IT2222889

申请日：1989-10-31

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CAPPELLETTI PAOLO ,  CORDA GIUSEPPE ,  GHEZZI PAOLO ,  RIVA CARLO ,  VAJANA BRUNO

IPC: G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866 ,  H01L

Abstract: The manufacturing process comprises a first step of formation of an N type sink (2) on a single-crystal silicon substrate (1), a second step of formation of an active area (14) on the surface of said sink (2), a third step of implantation of N- dopant in a surface region (4) of the sink (2) inside said active area (14), a fourth step of growth of a layer (5) of gate oxide over said region with N- dopant, a fifth step of N+ implantation (6; 9) inside said N- region, a sixth step of P+ implantation (7; 12) in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts (8, 18; 13, 23, 33) for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.

公开(公告)号：IT9019694A1

公开(公告)日：1991-09-16

申请号：IT1969490

申请日：1990-03-15

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CAPPELLETTI PAOLO ,  LUCHERINI SILVIA ,  VAJANA BRUNO

IPC: H01L21/8247 ,  H01L20060101 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115

公开(公告)号：DE69025854D1

公开(公告)日：1996-04-18

申请号：DE69025854

申请日：1990-10-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CAPPELLETTI PAOLO ,  CORDA GIUSEPPE ,  GHEZZI PAOLO ,  RIVA CARLO ,  VAJANA BRUNO

IPC: G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866 ,  H01L21/82 ,  H01L27/02 ,  G11C16/04

Abstract: The manufacturing process comprises a first step of formation of an N type sink (2) on a single-crystal silicon substrate (1), a second step of formation of an active area (14) on the surface of said sink (2), a third step of implantation of N- dopant in a surface region (4) of the sink (2) inside said active area (14), a fourth step of growth of a layer (5) of gate oxide over said region with N- dopant, a fifth step of N+ implantation (6; 9) inside said N- region, a sixth step of P+ implantation (7; 12) in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts (8, 18; 13, 23, 33) for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.

公开(公告)号：IT8922228D0

公开(公告)日：1989-10-31

申请号：IT2222889

申请日：1989-10-31

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CAPPELLETTI PAOLO ,  CORDA GIUSEPPE ,  GHEZZI PAOLO ,  RIVA CARLO ,  VAJANA BRUNO

IPC: G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866 ,  H01L

Abstract: The manufacturing process comprises a first step of formation of an N type sink (2) on a single-crystal silicon substrate (1), a second step of formation of an active area (14) on the surface of said sink (2), a third step of implantation of N- dopant in a surface region (4) of the sink (2) inside said active area (14), a fourth step of growth of a layer (5) of gate oxide over said region with N- dopant, a fifth step of N+ implantation (6; 9) inside said N- region, a sixth step of P+ implantation (7; 12) in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts (8, 18; 13, 23, 33) for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.