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    3.
    发明专利
    未知

    公开(公告)号：ITMI962742A1

    公开(公告)日：1998-06-24

    申请号：ITMI962742

    申请日：1996-12-24

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： DALLA LIBERA GIOVANNA ,  VAJANA BRUNO ,  BOTTINI ROBERTA ,  CREMONESI CARLO

    IPC: H01L21/336

    Abstract: A process for fabricating a memory cell having two levels of polysilicon and being included in a memory device of the EEPROM type, wherein the device is formed on a semiconductor material substrate which has a first conductivity type. The process comprises the steps of forming, on the substrate a thin tunnel oxide region surrounded by a gate oxide region previously formed on the same substrate, depositing a layer of polycrystalline silicon over the gate oxide region and the thin tunnel oxide region, and successively depositing a composite ONO layer and an additional polysilicon layer over the polycrystalline silicon layer. A capacitive implant mask having a window is formed by depositing a layer of a light-sensitive material over the additional polysilicon layer, a dopant is implanted through the window at an energy and with dosages effective to penetrate the polycrystalline silicon, ONO, and polysilicon layers, respectively, and a region of electric continuity is formed laterally and beneath the thin tunnel oxide region.

    5.
    发明专利
    未知

    公开(公告)号：ITMI962741A1

    公开(公告)日：1998-06-24

    申请号：ITMI962741

    申请日：1996-12-24

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： VAJANA BRUNO ,  CREMONESI CARLO ,  BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA

    IPC: H01L21/8247

    Abstract: A memory cell of the EEPROM type formed on a semiconductor material substrate having a first conductivity type includes a drain region having a second conductivity type and extending at one side of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region. The region of electric continuity is produced by implantation at a predetermined angle of inclination.

    6.
    发明专利
    未知

    公开(公告)号：IT1237666B

    公开(公告)日：1993-06-15

    申请号：IT2222889

    申请日：1989-10-31

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： CAPPELLETTI PAOLO ,  CORDA GIUSEPPE ,  GHEZZI PAOLO ,  RIVA CARLO ,  VAJANA BRUNO

    IPC: G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866 ,  H01L

    Abstract: The manufacturing process comprises a first step of formation of an N type sink (2) on a single-crystal silicon substrate (1), a second step of formation of an active area (14) on the surface of said sink (2), a third step of implantation of N- dopant in a surface region (4) of the sink (2) inside said active area (14), a fourth step of growth of a layer (5) of gate oxide over said region with N- dopant, a fifth step of N+ implantation (6; 9) inside said N- region, a sixth step of P+ implantation (7; 12) in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts (8, 18; 13, 23, 33) for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.

    10.
    发明专利
    未知

    公开(公告)号：DE69025854T2

    公开(公告)日：1996-08-01

    申请号：DE69025854

    申请日：1990-10-24

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： CAPPELLETTI PAOLO ,  CORDA GIUSEPPE ,  GHEZZI PAOLO ,  RIVA CARLO ,  VAJANA BRUNO

    IPC: G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866 ,  H01L21/82 ,  H01L27/02 ,  G11C16/04

    Abstract: The manufacturing process comprises a first step of formation of an N type sink (2) on a single-crystal silicon substrate (1), a second step of formation of an active area (14) on the surface of said sink (2), a third step of implantation of N- dopant in a surface region (4) of the sink (2) inside said active area (14), a fourth step of growth of a layer (5) of gate oxide over said region with N- dopant, a fifth step of N+ implantation (6; 9) inside said N- region, a sixth step of P+ implantation (7; 12) in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts (8, 18; 13, 23, 33) for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.

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