公开(公告)号：IT1294312B1

公开(公告)日：1999-03-24

申请号：ITMI971902

申请日：1997-08-07

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： BOTTINI ROBERTA ,  VAJANA BRUNO ,  DALLA LIBERA GIOVANNA ,  CREMONESI CARLO

IPC: H01L21/8247

公开(公告)号：ITMI962742A1

公开(公告)日：1998-06-24

申请号：ITMI962742

申请日：1996-12-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： DALLA LIBERA GIOVANNA ,  VAJANA BRUNO ,  BOTTINI ROBERTA ,  CREMONESI CARLO

IPC: H01L21/336

Abstract: A process for fabricating a memory cell having two levels of polysilicon and being included in a memory device of the EEPROM type, wherein the device is formed on a semiconductor material substrate which has a first conductivity type. The process comprises the steps of forming, on the substrate a thin tunnel oxide region surrounded by a gate oxide region previously formed on the same substrate, depositing a layer of polycrystalline silicon over the gate oxide region and the thin tunnel oxide region, and successively depositing a composite ONO layer and an additional polysilicon layer over the polycrystalline silicon layer. A capacitive implant mask having a window is formed by depositing a layer of a light-sensitive material over the additional polysilicon layer, a dopant is implanted through the window at an energy and with dosages effective to penetrate the polycrystalline silicon, ONO, and polysilicon layers, respectively, and a region of electric continuity is formed laterally and beneath the thin tunnel oxide region.

公开(公告)号：IT1289524B1

公开(公告)日：1998-10-15

申请号：ITMI962740

申请日：1996-12-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： VAJANA BRUNO ,  CREMONESI CARLO ,  BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA

IPC: H01L21/8247

公开(公告)号：ITMI962741A1

公开(公告)日：1998-06-24

申请号：ITMI962741

申请日：1996-12-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： VAJANA BRUNO ,  CREMONESI CARLO ,  BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA

IPC: H01L21/8247

Abstract: A memory cell of the EEPROM type formed on a semiconductor material substrate having a first conductivity type includes a drain region having a second conductivity type and extending at one side of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region. The region of electric continuity is produced by implantation at a predetermined angle of inclination.

公开(公告)号：ITMI971902A1

公开(公告)日：1999-02-08

申请号：ITMI971902

申请日：1997-08-07

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： BOTTINI ROBERTA ,  VAJANA BRUNO ,  DALLA LIBERA GIOVANNA ,  CREMONESI CARLO

IPC: H01L21/8247

公开(公告)号：IT1289526B1

公开(公告)日：1998-10-15

申请号：ITMI962742

申请日：1996-12-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： DALLA LIBERA GIOVANNA ,  VAJANA BRUNO ,  BOTTINI ROBERTA ,  CREMONESI CARLO

IPC: H01L21/336

Abstract: A process for fabricating a memory cell having two levels of polysilicon and being included in a memory device of the EEPROM type, wherein the device is formed on a semiconductor material substrate which has a first conductivity type. The process comprises the steps of forming, on the substrate a thin tunnel oxide region surrounded by a gate oxide region previously formed on the same substrate, depositing a layer of polycrystalline silicon over the gate oxide region and the thin tunnel oxide region, and successively depositing a composite ONO layer and an additional polysilicon layer over the polycrystalline silicon layer. A capacitive implant mask having a window is formed by depositing a layer of a light-sensitive material over the additional polysilicon layer, a dopant is implanted through the window at an energy and with dosages effective to penetrate the polycrystalline silicon, ONO, and polysilicon layers, respectively, and a region of electric continuity is formed laterally and beneath the thin tunnel oxide region.

公开(公告)号：ITMI962740A1

公开(公告)日：1998-06-24

申请号：ITMI962740

申请日：1996-12-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： VAJANA BRUNO ,  CREMONESI CARLO ,  BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA

IPC: H01L21/8247

公开(公告)号：IT1289525B1

公开(公告)日：1998-10-15

申请号：ITMI962741

申请日：1996-12-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： VAJANA BRUNO ,  CREMONESI CARLO ,  BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA

IPC: H01L21/8247

Abstract: A memory cell of the EEPROM type formed on a semiconductor material substrate having a first conductivity type includes a drain region having a second conductivity type and extending at one side of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region. The region of electric continuity is produced by implantation at a predetermined angle of inclination.