公开(公告)号：JPH05161094A

公开(公告)日：1993-06-25

申请号：JP17702891

申请日：1991-07-17

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FUABURITSUIO AIRORUDEI ,  FURANKO KABUAROTSUTEI ,  ARETSUSANDORO KUREMONESHI ,  JIYAN GUIDO RITSUTSUOTSUTO

IPC: H04N5/66 ,  H04N5/14 ,  H04N5/45 ,  H04N5/907 ,  H04N9/64

Abstract: PURPOSE: To reduce an access time to a memory by inputting pixels in parallel to the memory. CONSTITUTION: The device 1 is provided with 8-bit registers T1, T2, T3, T4 connected in cascade and an additional register T5. The register T1 receives a digital signal S1 at its input. The registers T1-T5 are configured to store one pixel of a video line. Thus, the array consisting of the registers T1-T4 accesses simultaneously four pixels, resulting that input signals are inputted in parallel. The register T5 stores an additional pixel and provides an output to an output RT. Memory banks L1, L2 being RAMs store one lie of a video frame. Each of the memories L1, L2 has a capacity of 320 cells (10). Each cell 10 has data inputs I1, I2 connecting to each output of the registers T1-T4.