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Patent Agency Ranking
公开(公告)号：JPH04211579A
公开(公告)日：1992-08-03
申请号：JP41301990
申请日：1990-12-25
Applicant: SGS THOMSON MICROELECTRONICS
IPC: H04N5/213
Abstract: PURPOSE: To reduce a pulse-type noise of a digital video receiver set by picking up a sample affected by the pulse-type noise and substituting this sample with a load average of samples in the band. CONSTITUTION: A noise reducer 6 is provided above a separator 4, and a demodulator 7 which takes a video signal 10 from an antenna 8 as the input and demodulates it is provided below the separator 4. The noise reducer 6 includes a digital decoder 9 so as to execute sampling of a video signal from the demodulator 7. A decoded signal 13 is sampled in this base band, and a load average is calculated based on the outline value. The sample value affected by a pulse-type noise is substituted with this load average.
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公开(公告)号：JPH05161094A
公开(公告)日：1993-06-25
申请号：JP17702891
申请日：1991-07-17
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： FUABURITSUIO AIRORUDEI , FURANKO KABUAROTSUTEI , ARETSUSANDORO KUREMONESHI , JIYAN GUIDO RITSUTSUOTSUTO
Abstract: PURPOSE: To reduce an access time to a memory by inputting pixels in parallel to the memory. CONSTITUTION: The device 1 is provided with 8-bit registers T1, T2, T3, T4 connected in cascade and an additional register T5. The register T1 receives a digital signal S1 at its input. The registers T1-T5 are configured to store one pixel of a video line. Thus, the array consisting of the registers T1-T4 accesses simultaneously four pixels, resulting that input signals are inputted in parallel. The register T5 stores an additional pixel and provides an output to an output RT. Memory banks L1, L2 being RAMs store one lie of a video frame. Each of the memories L1, L2 has a capacity of 320 cells (10). Each cell 10 has data inputs I1, I2 connecting to each output of the registers T1-T4.
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公开(公告)号：JPH036126A
公开(公告)日：1991-01-11
申请号：JP12560590
申请日：1990-05-17
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： JIYURIO FURIGERIO , ARETSUSANDORO KUREMONESHI
Abstract: PURPOSE: To speed up a conversion speed and to reduce power consumption by using plural comparing cells, successively determining four high order bits, reconverting the determined high order bits into analog bits, subtracting the analog bits from an input signal, and then determining four least significant bits(LSBs). CONSTITUTION: A comparing cell Cci is constituted of two capacitors Ci , C'i connected in series and a comparator Cpi . Input voltage Vi is transferred to the input Ii of each comparator Cpi by the capacitor Ci . When a switch SSIi is closed, the voltage Vi is connected to an output Ui and its offset is removed by the terminal of the comparator Cpi . At the time, the capacitor C'i is always grounded, the capacitor Ci is filled with reference voltage Vri and the most significant bit(MSB) is determined by the voltage variation (Vr -Vi ) of a branch point Ni . Then encoding logic LC detects the logical level of an output from the comparator Cpi , closes a selected switch SWi and determines the LSBs. Consequently the conversion speed can be increased and power consumption can be reduced.
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公开(公告)号：JPH02189017A
公开(公告)日：1990-07-25
申请号：JP32483989
申请日：1989-12-14
Applicant: SGS THOMSON MICROELECTRONICS
Abstract: PURPOSE: To reduce the storage capacity by connecting the output of each read amplifier, which corresponds to the most significant bit of each value, to a corresponding bit of a related adder and connecting other most significant input bits to all inputs. CONSTITUTION: Each line has a continuous partial product of variable word length. Since the word length is uniform in circuits on the outside of a memory M, it is necessary that bits deleted from words are added at the exit of the memory M to extend the reduced words. When 2's complement expression is selected for the partial product, the most significant bit of the word is repeated several times until the standard word length is obtained. A sum total Nb of required non-zero bits is Nb=b0 T-T /4 where T is the number of coefficients and b0 indicates the precision of the center coefficient. Thus, the number of one-bit cells is reduced by T /4, and it is reduced by 2N×T /4 in the whole of a 2N-line memory.
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公开(公告)号：JPH02189016A
公开(公告)日：1990-07-25
申请号：JP31634489
申请日：1989-12-05
Applicant: SGS THOMSON MICROELECTRONICS
Abstract: PURPOSE: To increase the speed and the performance by driving the address input of a memory cell by a sampled digital signal to be filtered and including a digital value, which is equal to the product of a preliminarily set coefficient and the address of each cell, in the memory cell of each bank. CONSTITUTION: Plural parallel adders are provided which have first and second inputs and outputs and are connected to the first input of an adder, to which parallel outputs of adders 2, 22...24 belong, through delay elements. The second input of each parallel adder is connected in parallel to the output of one of plural memory banks 40, 42, and 44, and memory banks 40, 42...44 have plural addressable memory cells. Address inputs can be driven by the sampled digital signal to be filtered, and each memory cell of each bank has the digital value equal to the product of the preliminarily set coefficient and the address of the cell. Thus, the speed and the performance are increased.
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