公开(公告)号：JPH036126A

公开(公告)日：1991-01-11

申请号：JP12560590

申请日：1990-05-17

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： JIYURIO FURIGERIO ,  ARETSUSANDORO KUREMONESHI

IPC: H03M1/14 ,  H03M1/36

Abstract: PURPOSE: To speed up a conversion speed and to reduce power consumption by using plural comparing cells, successively determining four high order bits, reconverting the determined high order bits into analog bits, subtracting the analog bits from an input signal, and then determining four least significant bits(LSBs). CONSTITUTION: A comparing cell Cci is constituted of two capacitors Ci , C'i connected in series and a comparator Cpi . Input voltage Vi is transferred to the input Ii of each comparator Cpi by the capacitor Ci . When a switch SSIi is closed, the voltage Vi is connected to an output Ui and its offset is removed by the terminal of the comparator Cpi . At the time, the capacitor C'i is always grounded, the capacitor Ci is filled with reference voltage Vri and the most significant bit(MSB) is determined by the voltage variation (Vr -Vi ) of a branch point Ni . Then encoding logic LC detects the logical level of an output from the comparator Cpi , closes a selected switch SWi and determines the LSBs. Consequently the conversion speed can be increased and power consumption can be reduced.