公开(公告)号：JPH08249239A

公开(公告)日：1996-09-27

申请号：JP34875795

申请日：1995-12-19

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： WUIDART SYLVIE

IPC: G06F12/14 ,  G06F15/78 ,  G06F21/06 ,  G06K19/073 ,  G07F7/10

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for improving the safety of an integrated circuit. SOLUTION: This method for improving the safety of the integrated circuit provided with at least one microprocessor and one or plural safety sensors C1-C3 for detecting an abnormal operating state and constituted so as to store the states of the respectively corresponding sensors by registers accessible by the microprocessor is presented. The method executes a read operation after the lapse of random time when the microprocessor receives an instruction for reading the register for at least one of the registers.

公开(公告)号：DE69501035T2

公开(公告)日：1998-03-05

申请号：DE69501035

申请日：1995-12-14

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： WUIDART SYLVIE

IPC: G06F12/14 ,  G06F15/78 ,  G06F21/06 ,  G06K19/073 ,  G07F7/10

Abstract: The process uses three security sensors (C1,C2,C3) to deliver binary data indicating a normal or alarm situation. The data is stored in an integral register to be read by the microcomputer. The timing of the readings is controlled by a pseudo random generator (GA) which is also contained in the integrated circuit. The integrated circuit includes a microprocessor (uP), a random access memory (RAM), a nonvolatile memory (E PROM) and the three security sensors. The first sensor (C1) detects too low a temperature, the second (C2) detects too low a frequency and the third (C3) detects supply overvoltage.

公开(公告)号：DE69501035D1

公开(公告)日：1997-12-18

申请号：DE69501035

申请日：1995-12-14

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： WUIDART SYLVIE

IPC: G06F12/14 ,  G06F15/78 ,  G06F21/06 ,  G06K19/073 ,  G07F7/10

Abstract: The process uses three security sensors (C1,C2,C3) to deliver binary data indicating a normal or alarm situation. The data is stored in an integral register to be read by the microcomputer. The timing of the readings is controlled by a pseudo random generator (GA) which is also contained in the integrated circuit. The integrated circuit includes a microprocessor (uP), a random access memory (RAM), a nonvolatile memory (E PROM) and the three security sensors. The first sensor (C1) detects too low a temperature, the second (C2) detects too low a frequency and the third (C3) detects supply overvoltage.

公开(公告)号：FR2765701B1

公开(公告)日：1999-08-20

申请号：FR9708444

申请日：1997-07-03

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： WUIDART SYLVIE

IPC: G06F12/16 ,  G06F11/00 ,  G06F11/36

Abstract: A detection circuit for access anomalies in microcontroller cell access consists of a central information processor (14), at least one RAM (18) of which part (26) is reserved for the cell, an input/output circuit (20) and a communication bus (22). The circuit incorporates a first detector 28) for all access to the cell (26), a second detector (32, 34) for any instruction giving access to the cell and an alarm signal generator (46) for when any access to the cell is detected outside an instruction containing such access. It also has a means (20) of interrupting the function of the micro-controller when an alarm signal is given.

公开(公告)号：FR2773625A1

公开(公告)日：1999-07-16

申请号：FR9800468

申请日：1998-01-13

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： WUIDART SYLVIE ,  LISART MATHIEU

IPC: G06F1/08 ,  H03K5/135 ,  G06F1/04 ,  H03K5/156 ,  G11C16/06

Abstract: The micro-controller integrated circuit has an internal clock generator (CKint) and a number of internal peripheral circuits (3,4,5) selectively activated by the microprocessor. The integrated circuit can adapt the period of the clock generator as a function of the operating time of the internal peripheral circuit which is activated by the processor.

公开(公告)号：FR2765701A1

公开(公告)日：1999-01-08

申请号：FR9708444

申请日：1997-07-03

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： WUIDART SYLVIE

IPC: G06F12/16 ,  G06F11/00 ,  G06F11/36

Abstract: A detection circuit for access anomalies in microcontroller cell access consists of a central information processor (14), at least one RAM (18) of which part (26) is reserved for the cell, an input/output circuit (20) and a communication bus (22). The circuit incorporates a first detector 28) for all access to the cell (26), a second detector (32, 34) for any instruction giving access to the cell and an alarm signal generator (46) for when any access to the cell is detected outside an instruction containing such access. It also has a means (20) of interrupting the function of the micro-controller when an alarm signal is given.

公开(公告)号：DE69600408T2

公开(公告)日：1998-10-29

申请号：DE69600408

申请日：1996-10-15

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： WUIDART SYLVIE

IPC: G11C19/00 ,  G11C19/28

公开(公告)号：DE69600376T2

公开(公告)日：1998-10-29

申请号：DE69600376

申请日：1996-10-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： WUIDART SYLVIE ,  SOURGEN LAURENT

IPC: H01L21/66 ,  H01L21/82 ,  H01L23/58

Abstract: The detection circuit has a pulse generator, which has a counter incrementing the pulse length of each pulse sent out. The pulse (Se) is applied to the integrated circuit via a snake shaped metallising line (2). The line forms a pass band filter with the passivation layer, and thus the short pulses are not received at the receiver (Sd) whilst longer pulses are. A correctly passivated integrated circuit can thus be determined from a tolerance threshold around the critical cut off pulse lengths.

公开(公告)号：DE69600148T2

公开(公告)日：1998-04-30

申请号：DE69600148

申请日：1996-03-19

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： SOURGEN LAURENT ,  WUIDART SYLVIE

IPC: G11C17/00 ,  G11C7/00 ,  G11C16/02 ,  G11C16/22 ,  G11C16/06

Abstract: The method involves using a high-voltage generator (1) and regulator (2) delivering the write pulse (Ve) to the memory address decoder (5) in response to a command (3) from a counter (9) initialised by a pseudo-random number generator (8). A microprocessor ( mu p) decodes a write instruction received via input/output signals (IO1,IO2) and reads the random number which is decremented to 1 at the rate of the clock (Clk). A constant delay between the external write command and the end-of-write signal is held in a memory (10) which activates another counter (11) and is programmed for each circuit.

公开(公告)号：FR2745099B1

公开(公告)日：1998-03-27

申请号：FR9602030

申请日：1996-02-19

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： WUIDART SYLVIE

IPC: G06F1/04 ,  G06F1/08 ,  G06K19/07 ,  G06K17/00 ,  G06K19/073

Abstract: An integrated circuit (1) receives an external clock signal (CK-ext) and in addition has a random generator (2) which produces a random clock signal (CK-al). The external and random clock signals are applied to a switching circuit (3). The switching circuit (3) is controlled by signals (K) from a group of circuits (5) including memories, data and processors and operates to select either the external or random clock signal for entry to the internal clock signal generator (4). The clock signal selection is such that the external signal is only used for external synchronisation.